Timeline for non-blocking assignment does not work as expected in Verilog
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Oct 8, 2013 at 6:13 | history | edited | Vasiliy | CC BY-SA 3.0 |
The first link is an outdated version of the second
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| Oct 8, 2013 at 2:12 | history | edited | travisbartley | CC BY-SA 3.0 |
Added alternative link to pdf and the title, in case the links die. I was having an issue getting it from the original link, but got it after about 10 tries.
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| Oct 8, 2013 at 1:15 | comment | added | travisbartley | Ah, this is a great point. I am not able to get the SNUG PDF, is there another link? | |
| Oct 7, 2013 at 12:45 | history | edited | Vasiliy | CC BY-SA 3.0 |
added 25 characters in body
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| Oct 7, 2013 at 12:34 | history | edited | Vasiliy | CC BY-SA 3.0 |
added 1 characters in body
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| Oct 7, 2013 at 11:50 | history | answered | Vasiliy | CC BY-SA 3.0 |