Timeline for Confusion over clocks in FPGAs / Verilog
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
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| Nov 24, 2013 at 20:16 | vote | accept | Void Star | ||
| Nov 24, 2013 at 13:55 | comment | added | Joe Hass |
You need to be more careful with your language in the question. Verilog statements may be evaluated (not executed) sequentially but synthesized into combinational logic. The term sequential logic is very confusing, and it's better to talk about combinational logic (AND, OR, NOT) or synchronous logic (flip-flops and latches).
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| Nov 24, 2013 at 13:52 | history | edited | Joe Hass | CC BY-SA 3.0 |
Corrected SI units, removed redundancy from title
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| Nov 24, 2013 at 9:55 | answer | added | alex.forencich | timeline score: 8 | |
| Nov 24, 2013 at 5:08 | answer | added | user30985 | timeline score: 1 | |
| Nov 24, 2013 at 4:04 | comment | added | Void Star | I think the problem is that I bear the nature of hardware description languages in mind too heavily. I was expecting everything to be building modules out of combinational logic and working up from there (or top down, but ultimately down to the logic level). I was very surprised to see there were sequential elements to Verilog, so I am still trying to wrap my brain around that, and figuring out how it synthesizes this sequential logic. And yes, that search was very illuminating. | |
| Nov 24, 2013 at 3:39 | comment | added | JustJeff | always bear in mind when you're working with verilog or vhdl, you're providing a description of hardware in what looks like code, not actually coding. everything happens at the same time unless you make an effort to make things sequential. As for clock multiplication, a search on phase locked loops (PLLs) will be illuminating. | |
| Nov 24, 2013 at 2:51 | history | asked | Void Star | CC BY-SA 3.0 |