Timeline for Gated clocks and clock enables in FPGA and ASICS
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Jan 20, 2015 at 21:05 | comment | added | supercat | ...those anti-phase cycles where either the CPU wants to talk to the UART, the synchronizer's output has changed, or the UART knows something useful is happening. On a lot of chips clocking the UART adds noticeably to the power consumption; it would seem that gating the clock should make it possible to eliminate most of that cost with no penalty other than, perhaps, needing to add an extra wait state on register reads and/or writes. | |
| Jan 20, 2015 at 21:03 | comment | added | supercat | I wonder why I don't hear of such an approach being used terribly often? I would think that in something like an ARM, having peripheral subsystems run off a clock which was anti-phase of the main clock would make it easier to refrain from clocking the bulk of a subsystem if it doesn't have anything useful to do and the main CPU doesn't want to talk to it. If e.g. a UART doesn't have anything going on, it shouldn't be necessary to clock most of its registers during each cycle. Simply clock an input-synchronizer on the same clock edges as the main CPU, and clock the UART on... | |
| Dec 20, 2013 at 5:28 | history | edited | Marcus10110 | CC BY-SA 3.0 |
fixed formatting at the top.
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| Dec 20, 2013 at 5:23 | comment | added | Marcus10110 | That's an example of synchronous clock domains, where the two clocks are related to each other. Then all you need is to-from constraints with the minimum time between valid edges, in this case half the period (if the clock has a 50% duty cycle) | |
| Dec 18, 2013 at 21:43 | comment | added | supercat | It would seem like, in many cases, one should be able to fairly easily guarantee that two clock domains will never have an active clock edge anywhere near each other. For example, one could have one clock domain respond to the rising edge of a master clock, and have another clock domain respond to any falling edge of the master clock which occurs when a particular output from the first domain is set. The propagation-delay allowance when crossing between domains would be much less than within a domain, but other than that what problems would there be? | |
| Dec 11, 2013 at 9:31 | history | answered | Marcus10110 | CC BY-SA 3.0 |