Timeline for How does the DDR clock compensation capacitor improve signal quality?
Current License: CC BY-SA 3.0
6 events
when toggle format | what | by | license | comment | |
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Mar 28, 2014 at 18:55 | comment | added | ajs410 | I think loading more means that the fanout of the clock pin is high. | |
Jan 1, 2014 at 12:59 | comment | added | user19579 | if perfect answer is required, This should be decided by simulation. We have used this Ccomp for 9 loads (x8). | |
Jan 1, 2014 at 10:42 | comment | added | YNWA | Hi :) what do you mean by "when loading is more" ? | |
Dec 30, 2013 at 6:00 | comment | added | user19579 | Shunted Capacitor is mentioned in DDR app notes..it is mentioned for single ended signals.for differential signals like DDR3 Clock capacitor will be connected parallel to CK- and CK+. It mainly recommneded when loading is more. we have used them when we are using 9 x8 DDR3 chips for each DDR3 controller. AN520 from Altera is having few words on this. | |
Dec 28, 2013 at 8:38 | comment | added | YNWA | hi, they are talking about a shunted capacitor to ground, I was talking about a capacitor placed between the differntial clock signals. (the capacitors sizes are different also, ~uF vs. ~pF) | |
Dec 28, 2013 at 3:59 | history | answered | user19579 | CC BY-SA 3.0 |