Visualising redundancy in a 1.5 bit pipeline ADC

Question

In a pipeline ADC, we have redundancy where we increase number of levels to somehow more accurately measure the input and reduce the error.

In the manual shown below we see a redundancy example from a Maxim tutorial.

They don't show in the example how exactly given an error the redundancy fixes it.

They only say that we fix the problem by doing right shift to the bits and summing the stages data. I think digital fixing is not redundancy. I can't see how in case of an error redundancy helps me with figuring the correct location of digital value.

https://www.maximintegrated.com/en/design/technical-documents/tutorials/1/1023.html

Answer 1

You can see the advantage of the redundant bits with a simple example where normal pipeline ADC fails bit the 1.5 bit pipeline gives the correct digital code corresponding to the analog input.

Consider a normal pipeline ADC, without any redundant bits. The Multiplying Digital to Analog Converter (MDAC) characteristics (fully differential) would look as shown below (Vref is assumed to be 1V):

If the input voltage is 0.6V, then, based on the above MDAC characteristic, the output code would be, 1100110.

Vin    Digital Code    Vres
+0.6     1              2x0.6-1 = 0.2
+0.2     1              2x0.2-1 = -0.6
-0.6     0              2x-0.6+1 = -0.2
-0.2     0              2x-0.2+1 = 0.6
+0.6     1              2x0.6-1 = 0.2
+0.2     1              2x0.2-1 = -0.6
-0.6     0              2x-0.6+1 = 0.2

In decimal system 1100110 is 102 which corresponds to \$\frac{102X2}{128}-1 = 0.59375V\$.

Now, suppose the comparator has an offset of 0.21V, the MDAC characteristics would now look like the red curve as shown below. The MDAC might produce an output outside the ADC reference range called the overrange error.

Consider same input to the ADC again, the output code would be 101111 (95 LSB).

Vin    Digital Code    Vres
+0.6     1              2x0.6-1 = 0.2
+0.2     0              2x0.2+1 = 1.4
+1.4     1              2x1.4-1 = 1.8
+1.8     1              2x1.8-1 = 2.6
+2.6     1              2x2.6-1 = 4.2
+4.2     1              2x4.2-1 = 7.4
+7.4     1              2x7.4-1 = 13.8

Thus any offset in the comparator might result in overrange error and would give incorrect digital code for the analog input.
Consider now the case with 1.5bit pipeline ADC with one of the comparators having 0.21V offset error. The MDAC characteristics would now look as follows:

Clearly the residue voltage always stays within the reference range and there are no overrange errors. In the 1.5 bit pipeline ADC, any comparator has offset within \$\pm \frac{V_{ref}}{4}\$ can be corrected without any overrange error.
If 0.6V input is applied to this ADC, the output code is 1001100.

Vin    Digital Code    Vres
+0.6     1              2x0.6-1 = 0.2
+0.2     0              2x0.2 = 0.4
+0.4     0              2x0.4 = 0.8 --> Incorrect bit due to comparator offset
+0.8     1              2x0.8-1 = 0.6
+0.6     1              2x0.6-1 = 0.2
+0.2     0              2x0.2 = 0.4
+0.4     0              2x0.4 = 0.8

The decimal value corresponding to 1001100 is 76 which is \$\frac{76}{128} = 0.59375V\$, same as before.
Besides offset, overrange errors could also result from gain mismatch inside the MDAC. The redundant bits make the design more tolerant of such errors.
Similar schemes also exist for SAR ADC where extra compensation bits (extra capacitors in the capacitive DAC) are added which can allow the design to be more tolerant to the DAC settling errors. But the output latency is increased since extra clock cycles need to be added for the digital output. There are binary and non-binary compensation techniques. But I will leave their explanation for later.

Answer 2

The 1,5 bit adc stage gives you some tolerance e.g. for inaccuracy of the reference voltage. If you combine 2 stages with 1,5 bits each in a clever manner you get 2 bits + 1LSB which might be instable... so you just throw it away.

so that 0,5 bit is just a safety reserve to achieve better precision

Answer 3

This is hopefully an answer to the question here, but it is also a follow up to the comments in What is the meaning of handling error in 1.5 bit ADC?

Here is an example for a 3 bit ADC with 1.5bit stages. The output range is "0".."7" (bits 2, 1 and 0 as "000" ... "111").

To make the explanation easier, let's set thresholds at 1V,2V,..6V. Perhaps you know this is not ideal, and that the usual thresholds are (0.5...6.5)*Vrange, but the simplified thresholds make the example easier without losing the salient feature of a 1.5bit ADC.

Remember, this ADC is not about better quantization, but about allowing for tolerances for threshold and subtraction voltages. So we will allow ourselves to use a "floor" type ADC since it makes the example easier, although it is worse for quantization.

Take an input of Vi 4.1V.

1. An ADC with non-overlapping stages decides in stage 1 (MSB, bit nr 2) that Vi >= 4V, and sets bit 2 to "1". (If it's <4V we set it to "0", so it shows you we are flooring.)
2. Subtract 4 for the next stage, to get 0.1V < 2V, so bit 1 is set to "0".
3. Subtract 0 for the next stage, to get 0.1V < 1V so bit 2 is set to "0" and the output is "100" or "4".

A 1.5 bit stage is more cautious about stage input levels that are around the threshold.

This is an example of the principle, and so I am omitting amplifiers in each stage, which normalize voltages in stages within ranges like 0...1V. I think it will better illustrate what is going on, and you don't have to mentally re-scale to recognize the numbers.

1. 4.1 is around threshold 4, so bit 2 is "X", where "around" means 2 <= V < 6
2. Subtract 2 (not 4) because of previous "X" , to get 2.1. It's around threshold 2, with 1 <= V <3 so bit 1 is also "X".
3. Subtract 1 (not 2) because of previous "X" , to get 1.1. The last bit is a 1-bit stage, and decides <1 or >=1. It's 1.1 >= 1 so bit 3 is 1.

Now we have "XX1". This means 2 <= Vin < 6, 1 <= Vin-2 < 3 and Vin-2-1 >= 1.

Note that the "XX1" does not mean that the output will be "??1". It is only a way to encode the decisions. We could also write "XX+" or "XX>".

So "XX1" is Vin=2..5, Vin=3..4, and Vin>=4.

Conclusion: Vin=4 (quantized) and so output is "100".

Another example, now with Vin=6.1

1. Vin>=6, bit 2 = "1", subtract 4
2. 6.1-4 = 2.1, with 1 <= 2.1 < 3 , bit 1 = "X", subtract 1
3. 2.1-1 = 1.1 >= 1, bit 0 = "1".

Now we have "1X1". This means V = 6..7, Vin = 5..6, Vin >= 6.

Conclusion: Vin=6 (quantized) and so the output is "101".