Quick answer - a FET is not a bipolar transistor.
Vth relates to the minimum voltage present between Gate and Source: Vgs(threshold) if you like. The voltage present at the source will depend on the resistance between source and drain for that particular Vgs.
For an N FET, the diagram you have will not work. If the Source voltage approached the Drain voltage and the Gate voltage is also the Drain voltage, then Vgs -> 0. You need a P FET and you need the Gate to be closer to 0V.
Edit: Roger C's answer assumes something I didn't - that the voltage on the right (Vdd - Vth) is being held at that potential by an external reference. In that case, the illustration is correct (the maximum possible voltage at the source is VDD-Vth, otherwise the NMOS would be OFF).