I find myself in a similar situation, Ironstein. In my application I need to support Spartan-6 FPGAs (requiring use of XST) and also Artix-7 FPGAs (requiring Vivado in some cases, and XST or Vivado with other models). I’ve become facile with the memory and clock management tiles.
I agree with your assessment that using IPcores is easiest, but then from a project management standpoint I find it can become tricky to manage as there are so many files which need to be at the correct location 'just so'. I prefer to only use IPcores to instantiate distributed memory elements.
I am a bit wary of inferred designs in general as the slightest change may 'break' the DSP architecture, or some of the subtleties of how registers are allocated as Alex.Forencich pointed out.
I prefer to have explicit control of precisely what is going on, and so I am on the arduous learning curve to understanding the DSP48A1 block, and the related macro blocks: ADDMACC_MACRO, ADDSUB_MACRO, COUNTER_LOAD_MACRO, MULT_MACRO, and MACC_MACRO. These macros address common functions which can get you started without having to know all of the complexity of the full DSP48A1 primitive of the Spartan-6 family.
You can find VHDL/Verilog templates for the DSP48A1 primitive and these macros in the UG615 user guide as has been suggested. However, these templates are long enough that I prefer to make use of the Language Templates feature in XST to more directly copy/paste them into my designs. That's accessed via the "Edit > Language Templates… > VHDL || Verilog > Device Macro Instantiation" (for macros) or "Edit > Language Templates… > VHDL || Verilog > Device Macro Primitives" (for the primitive modules). You then select the FPGA family and DSP, and you're all set. Since my designs also span the Spartan-6 / Artix-7 families that are supported by XST, I find the Language Templates feature to be quite handy.