The problem with Double-Dabble is that it was written for software programs, so the solution is inherently serial. FPGA's and ASIC's are parallel in nature: we need to use their strengths to our advantage.
While Double-Dabble works, the example given here uses 11 clock cycles after initialization to arrive at a 3-digit result from an 8-bit input. For an 8-digit result from a 27-bit input Double-Dabble requires 35 clock cycles. A reachable goal for an N-digit result is N-1 clock cycles. How? By doing long division in parallel.
For an eight digit result from a 27-bit input, start by doing 9 subtractions in parallel, input1 minus: 9000_0000, 8000_0000, 7000_0000, ..., 2000_0000, 1000_0000 and implicit 0. Take the remainder from largest factor where the result is not negative (test the top bit of the result), record the factor as the top digit and use the remainder as the input to the next stage, which is again 9 subtractions in parallel. Input2 minus 900_0000, 800_0000, 700_0000, ..., 200_0000, 100_0000 and implicit 0. Repeat this procedure down to input7 minus 90, 80, 70, ..., 20 and 10. The remainder from the last subtraction is the one's digit.
Using this method requires seven clock cycles after initialization for an eight digit result. Depending on the FPGA, this might be implemented with nine DSP's and 63 constants. Without DSP's, the number of bits of subtraction go down by three or four bits on every cycle, so it does not take as much fabric as you might expect, and it still only requires seven clock cycles to complete.