Short answer: for the BJT output, it’s actually the base-emitter current that turns on the transistor, not collector current. Likewise, for the FET it’s the gate-source voltage, not gate-drain voltage.
A way to think of it is take note of the impedance of the open-collector / open-drain signal without benefit of a pull-up:
- BJT with Vce in forward bias: collector is low impedance
- BJT with Vce not forward biased: collector is high impedance.
Same thing with the FET with its gate-drain voltage in its on and off state.
Now, the thing about the impedance behavior is that it doesn’t care about the actual voltage of the driven line (within limits, see at the end.)
In both cases, when the driver transistor is off, the line floats. What it floats to depends largely on what’s attached to it.
If it’s just capacitance like with shown in your simulation, it will remain near your negative rail.
If you were to connect a logic IC you would connect your comparator (-) supply to GND, not -5V. Let’s assume you’ve done that. Then:
If the load is a MOS IC the line will reach some mid-level due to the IC’s input protection diode leakage. You won’t see this in your sim unless you turn off the driver and wait for a very, very long time (on the order of seconds.) Even then, the driver has its own leakage which will also influence the final settled voltage.
If the load is a TTL IC input (typically an NPN emitter) the pin will source a small current to Vcc, bringing the undriven line to about 3V.
About that ‘within limits’ above. Assume (-) supply is GND. With a floating line, even in the off state (base or gate at ground), the BJT and FET will clamp any below-ground voltage to nearly ground:
- grounded base of NPN BJT forms forms a collector-base diode to ground. Output will be clamped to no more than -0.5V or so.
- off-state n-FET has a parasitic drain-source body diode. Again, output will be clamped to no more than -0.5V.
In other words, you will see no more than one diode drop below ground, or whatever the (-) supply pin is.