I did find a minimization error. See below.
some initial thoughts
A 7447 7-seg decoder uses 4 binary inputs, not 3. But I take it that this is to be only have 3 binary inputs and works only for 0 to 7. (No 8 or 9 is available.)
Also, I think I see in the problem statement that you aren't supposed to actually use a 3-to-8 decoder module, but instead you are supposed to build a 3-8 decoder out of AND and OR gates, with NOT allowed.
This leaves open a question in my mind. A natural assumption that experienced designers would make is that a 3-to-8 decoder is a very specific thing. But, technically, I could make a 3-to-8 decoder that produces A-to-G outputs for a 7-segment display and add an 8th output that is always '0' or always '1' and it would still be a decoder and more specifically it would be a 3-to-8 decoder in every possible meaning of the phrase. Just not the 3-to-8 decoder that one would normally think of when seeing the phrase. Still, I could make a very strong argument that this term allows my specific interpretation in this specific case.
So this leaves me not wanting to go down that rabbit hole and to instead drill in on your k-maps.
k-maps
In looking over your k-maps, I believe I may have found an error. Here's the table I used:
The above matches your table. (Well, I copied it from your table so I hope so.)
Here's the error. It's C's table:
So, the logic here is \$C=S_1 + \overline{S_2} + S_3\$. That's the only error I found.
There is another note, though:
Here's another way to see G:
That's not better than what you did (which is correct.) It's just another way to see it done, in case it helps.
(I used Neemann's Digital software to produce the above table and k-maps.)