Timeline for 125 MHz parallel bus in a double 2.54mm header
Current License: CC BY-SA 3.0
14 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 27, 2014 at 8:20 | vote | accept | Blup1980 | ||
| Apr 24, 2014 at 15:44 | answer | added | Martin Thompson | timeline score: 1 | |
| Apr 18, 2014 at 14:11 | comment | added | user19579 | @Blup1980: It's ok, i can't frame proper answers. can give comments. | |
| Apr 18, 2014 at 10:25 | comment | added | Blup1980 | @user19579 Other answer are good too but your comment is the most useful to me, I think. You should convert it to an answer and I will accept it. | |
| Apr 17, 2014 at 8:28 | history | tweeted | twitter.com/#!/StackElectronix/status/456710727500185600 | ||
| Apr 17, 2014 at 7:59 | comment | added | user19579 | Try to get the RLC model of the connector from tyco or samtec. You can simulate the whole path. suggestion is altera very good company without proper thought they will not include these headers in to the board and Differential traces will be more tolerant to SI compared to Single ended signals.I have just downloaded Single line Model of AMPMODU type connector and see R=12m,L=2.5n,C=0.6p--> These values are very less. They will not cause much loading. Tpd is around 39ps which is also very less. | |
| Apr 17, 2014 at 7:44 | comment | added | user19579 | Try to get the RLC model of the connector from tyco or samtec. You can simulate the whole path. suggestion is altera very good company without proper thought they will not include these headers in to the board and Differential traces will be more tolerant to SI compared to Single ended signals. | |
| Apr 17, 2014 at 7:35 | answer | added | Kamil | timeline score: 4 | |
| Apr 17, 2014 at 7:17 | comment | added | markt | Given that they're differential traces, and given the likely LVDS signalling capabilities of the FPGA, I'd expect them to work perfectly well up to several hundred MHz if not a GHz or so. Also, you could always ask the vendor of the board. | |
| Apr 17, 2014 at 7:13 | comment | added | Blup1980 | I see your point. But I hove not idea of the max speed of that connector. They may have routed the board that way having 30MHz signals in mind. Who knows? This is not documented. And because this is logic signalling. The frequency content of the signal is defined by the rise time that may end up to 500MHz+ of required bandwidth. But even at those frequencies, the length of the connector is small regarding lambda max (no ribbon cables). Thus I don't know what to think. | |
| Apr 17, 2014 at 7:05 | comment | added | markt | The question you should ask yourself is, why would the designer expend the effort to route the signals, particularly all the fiddling with matched lengths and impedance control, if they didn't expect it to work? The short answer is, it should work perfectly well - especially if you take the same kind of care with your daughter board. | |
| Apr 17, 2014 at 7:05 | history | edited | Blup1980 | CC BY-SA 3.0 |
deleted 3 characters in body; edited title
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| Apr 17, 2014 at 6:34 | history | edited | Blup1980 | CC BY-SA 3.0 |
typos + link to datasheet
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| Apr 17, 2014 at 5:29 | history | asked | Blup1980 | CC BY-SA 3.0 |