Timeline for Is there a more optimized way of making an incrementer than a full adder?
Current License: CC BY-SA 2.5
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 12, 2017 at 11:13 | answer | added | user2472001 | timeline score: 0 | |
| Apr 4, 2011 at 1:45 | comment | added | Kortuk | @JaimePardos, all ALUs use this or a more advanced device to increase speed. Waiting for 32 carry bit delays is not acceptable in a modern processor. | |
| Apr 4, 2011 at 1:07 | answer | added | BarsMonster | timeline score: 1 | |
| Apr 3, 2011 at 12:17 | comment | added | raven | BTW: link just in case en.wikipedia.org/wiki/Carry_look-ahead_adder | |
| Apr 3, 2011 at 12:17 | comment | added | raven | I don't know almost anything about VHDL and maybe you take this for granted when you talk about a full adder, so sorry if that's the case, but for improving performance you have the "carry look-ahead adder". | |
| Apr 3, 2011 at 11:01 | answer | added | freespace | timeline score: 2 | |
| Apr 3, 2011 at 7:00 | vote | accept | Earlz | ||
| Apr 3, 2011 at 6:08 | history | tweeted | twitter.com/#!/StackElectronix/status/54425120671928321 | ||
| Apr 3, 2011 at 5:27 | answer | added | user3624 | timeline score: 9 | |
| Apr 3, 2011 at 2:51 | answer | added | CoderTao | timeline score: 3 | |
| Apr 3, 2011 at 2:32 | history | asked | Earlz | CC BY-SA 2.5 |