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I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opinion, this is not satisfying.

Reviewing the literature it seems that System Generator for DSP by Xilinx is quiet popular at the moment for automated FPGA implementation out of Simulink.

My question is: How does SG actually works? Does it only combine pre-defined IP cores according to model scheme or does it really compile VHDL code of the system? Is there any chance to at least "have a look" to the inner HDL description of the blocks?

I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opinion, this is not satisfying.

Reviewing the literature it seems that System Generator for DSP by Xilinx is quiet popular at the moment for automated FPGA implementation out of Simulink.

My question is: How does XSG actually works? Does it only combine pre-defined IP cores according to model scheme or does it really compile VHDL code of the system? Is there any chance to at least "have a look" to the inner HDL description of the blocks?

I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opionion, this is not satisfying.

Reviewing the literature it seems that System Generator for DSP by Xilinx is quiet popular at the moment for automated FPGA implementation out of Simulink.

My question is: How does SG actually works? Does it only combine pre-defined IP cores according to model scheme or does it really compile VHDL code of the system? Is there any chance to at least "have a look" to the inner HDL description of the blocks?

I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opinion, this is not satisfying.

Reviewing the literature it seems that System Generator for DSP by Xilinx is quiet popular at the moment for automated FPGA implementation out of Simulink.

My question is: How does SG actually works? Does it only combine pre-defined IP cores according to model scheme or does it really compile VHDL code of the system? Is there any chance to at least "have a look" to the inner HDL description of the blocks?

I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opionion, this is not satisfying.

Reviewing the literature it seems that System Generator for DSP by Xilinx is quiet popular at the moment for automated VHDL code generatation out of Simulink.

My question is: How does SG actually works? Does it only combine pre-defined IP cores according to model scheme or does it really compile VHDL code of the system? Is there any chance to at least "have a look" to the inner HDL description of the blocks?

I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opionion, this is not satisfying.

Reviewing the literature it seems that System Generator for DSP by Xilinx is quiet popular at the moment for automated FPGA implementation out of Simulink.

My question is: How does SG actually works? Does it only combine pre-defined IP cores according to model scheme or does it really compile VHDL code of the system? Is there any chance to at least "have a look" to the inner HDL description of the blocks?