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I'm developing control algorithms on FPGAs. By now, we use hand-written VHDL code for our fundamental entities we combine to more complex IPs, all done manually. In my opinion, this is not satisfying.

Reviewing the literature it seems that System Generator for DSP by Xilinx is quiet popular at the moment for automated FPGA implementation out of Simulink.

My question is: How does XSG actually works? Does it only combine pre-defined IP cores according to model scheme or does it really compile VHDL code of the system? Is there any chance to at least "have a look" to the inner HDL description of the blocks?

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  • \$\begingroup\$ I'm not familiar with system generator, but I think there are 3 possibilities here. 1) is that it skips the HDL step and just produces a netlist 2) is that it produces HDL that will be very confusing for a human to read and 3) is that it is intentionally obscured in order to prevent you from using it with FPGAs from other manufacturers \$\endgroup\$ – kjgregory Mar 17 '15 at 13:30
  • \$\begingroup\$ I agree. I'm using Qsys tool from Quartus II a lot, whose output is basicly an HDL file with an instance of all IPs you included. The actual HDL files for the IP are just copied and then Quartus takes over to perform the synthesis. I wonder if XSG is similiar. \$\endgroup\$ – Clemens Mar 17 '15 at 16:20
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Sys-gen, as well as Simulink creates HDL code. However, sys-gen utilizes/assigns available DSP blocks, memories, and other blocks available in the specific FPGA to maximize the implementation efficiency. The great advantage of it is that you might not need to look at the HDL script - you can program the FPGA directly (with the help of the ISE suite). It also allows real time simulation. There's a lot to it. You should just watch demos and introductory videos.

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  • \$\begingroup\$ Thanks for your input. In general, my question arises because I research approaches for automated HDL generation. Our hand-written basic entities (like add/mult, controller, limiter,...) are working fine and somehow efficient, sow we still want to use exactly them but we need an easier way for configuration of a whole system \$\endgroup\$ – Clemens Mar 20 '15 at 8:16

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