Timeline for How to reduce SPI bit errors between a Bus Pirate and a BIOS chip?

11 events

when toggle format	what		by	license	comment
Nov 4, 2015 at 17:29	comment	added	Tom Carpenter		SPI mode is correct. The bios chips supports Mode 0 and Mode 3. You settings are Mode 0 (CPOL=0, CPHA=0). Note that "Active to Idle" means the edge where the clock goes from its active value to its idle value (the idle value being the clock polarity setting).
Nov 4, 2015 at 17:20	history	edited	Richard Hansen		tags
Nov 4, 2015 at 17:14	history	edited	Richard Hansen		add more tags
Nov 3, 2015 at 4:32	history	edited	Richard Hansen	CC BY-SA 3.0	deleted 18 characters in body
Nov 3, 2015 at 4:21	history	edited	Richard Hansen	CC BY-SA 3.0	clarify SPI settings
Nov 3, 2015 at 0:58	comment	added	Richard Hansen		@crasic: Updated my question.
Nov 3, 2015 at 0:58	history	edited	Richard Hansen	CC BY-SA 3.0	add SPI settings
Nov 3, 2015 at 0:51	comment	added	crasic		Are you sure you are using the right SPI mode?
Nov 3, 2015 at 0:49	history	undeleted	Richard Hansen
Nov 3, 2015 at 0:49	history	deleted	Richard Hansen		via Vote
Nov 3, 2015 at 0:48	history	asked	Richard Hansen	CC BY-SA 3.0