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Timeline for discharge power rail with MOSFET

Current License: CC BY-SA 3.0

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Nov 18, 2015 at 10:34 answer added Autistic timeline score: 0
Nov 18, 2015 at 7:09 answer added user57037 timeline score: 1
Nov 18, 2015 at 2:32 review Close votes
Dec 4, 2015 at 3:02
Nov 17, 2015 at 22:25 comment added jsmith To mkeith, it's not open-collector.. The WD timer drives 5V or low. The signal cannot be high when the 3.8V rail is low because the signal high will enable the 3.8V regulator
Nov 17, 2015 at 22:19 comment added user57037 And the active low signal, is it open-collector with pullup, or is it driven high? If it is driven high, what voltage is it driven to? If it is pulled up, what voltage is it pulled up to? Finally, and this is very important, can the active low signal be HIGH when the 3.8V rail is LOW? Or does it depend on the 3.8V rail for power?
Nov 17, 2015 at 21:49 comment added jsmith ~500uF on the rail
Nov 17, 2015 at 21:49 history edited jsmith CC BY-SA 3.0
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Nov 17, 2015 at 21:01 comment added user57037 This is easily done. But we need to know how much capacitance is being drained off. There could also be a sequencing issue here. Where does the active low signal come from? Does it rely on the 3.8V rail for power? If so, you will need to think this through carefully.
Nov 17, 2015 at 20:59 comment added Andy aka What capacitance are you discharging and what is the normal current consumption of the circuit that gets discharged. What is the control signal. What is the device that disconnects power so that you can adequately discharge the residual power? What is an acceptable level to discharge to in 200 ms (don't say 0V because discharging a cap to zero takes infinite time with a simple circuit).
Nov 17, 2015 at 20:44 comment added EM Fields If the control signal is already active low, why not just use a PFET to do the job?
Nov 17, 2015 at 20:25 review First posts
Nov 18, 2015 at 9:08
Nov 17, 2015 at 20:17 history asked jsmith CC BY-SA 3.0