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I need to discharge a power rail from 3.8V to 0V within 200ms. The control signal is active low (i.e. start discharging when control becomes low). I think the easiest implementation probably is to use NFET and invert the control signal to feed the gate. That means I need an inverter + NFET. Any single IC that can achieve this function?

In detail, the control signal comes from a watchdog timer, which is powered by a different power supply. The signal will hold low ~200ms and disable 3.8V regulator meanwhile, and then go back high and enable the regulator again. I plan to use this signal to discharge the 3.8V rail at the same time. I can't use PFET because it will stop discharge (~0.7V) when Vgs<-Vt. My concern is if I don't discharge the rail to GND, I am not sure if the logic circuits can power up to the right states every time the power is cycled. Can these residue voltages inside the ICs cause, say, latch up or other unintentional shorts? Thanks.

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    \$\begingroup\$ If the control signal is already active low, why not just use a PFET to do the job? \$\endgroup\$
    – EM Fields
    Nov 17, 2015 at 20:44
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    \$\begingroup\$ What capacitance are you discharging and what is the normal current consumption of the circuit that gets discharged. What is the control signal. What is the device that disconnects power so that you can adequately discharge the residual power? What is an acceptable level to discharge to in 200 ms (don't say 0V because discharging a cap to zero takes infinite time with a simple circuit). \$\endgroup\$
    – Andy aka
    Nov 17, 2015 at 20:59
  • \$\begingroup\$ This is easily done. But we need to know how much capacitance is being drained off. There could also be a sequencing issue here. Where does the active low signal come from? Does it rely on the 3.8V rail for power? If so, you will need to think this through carefully. \$\endgroup\$
    – user57037
    Nov 17, 2015 at 21:01
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    \$\begingroup\$ ~500uF on the rail \$\endgroup\$
    – jsmith
    Nov 17, 2015 at 21:49
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    \$\begingroup\$ To mkeith, it's not open-collector.. The WD timer drives 5V or low. The signal cannot be high when the 3.8V rail is low because the signal high will enable the 3.8V regulator \$\endgroup\$
    – jsmith
    Nov 17, 2015 at 22:25

2 Answers 2

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Since you are actively driving the enable to either 0 or 5V, and since the control signal is always valid, even before 3.8V is enabled, you can just use PMOS with a current limiting resistor. I would select the resistor so that the RC is around 20 ms. This way, after 200 ms, you will go through 10 time constants. The rail will be pretty low. Here is the circuit.

schematic

simulate this circuit – Schematic created using CircuitLab

One problem with this is that it will only drain until it reaches the Vgs(th) of the transistor. If that is not desirable, you can use your original idea of pulling it down with NMOS. You would need to invert the signal. Make sure you drive the NMOS gate with 5V so that is is on hard regardless of the voltage decay of the 3.8V rail.

Anyway, if you use the above, you can probably use any power rating resistor you want, assuming the 3.8V rail is de-activated, and the FET will not be turned on in a high cycle fashion. If you do need to cycle rapidly, use a real power FET and a 0.5W resistor.

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The discharge current needed is not high .In fact 200mA would be more than enough .So use a sinple cheap BJT current sink which will linearly pull the rail down untill about 1v or so where the current starts to fall .The point is that here a BJT will outperform a mosfet.

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  • \$\begingroup\$ PNP will force the control signal to sink current. Be sure to limit it to a reasonable value with an appropriate base resistor. \$\endgroup\$
    – user57037
    Nov 19, 2015 at 4:16

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