Timeline for What will the output of filp-flop if its input is metastable?
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jun 9, 2016 at 12:43 | vote | accept | tollin jose | ||
| May 10, 2016 at 13:02 | comment | added | Wouter van Ooijen | Yes. Or (on a bad day) it could still be metastable. | |
| May 10, 2016 at 12:32 | comment | added | tollin jose | In this figure they got logic one at the output. Is it just an assumption ? it can settle to logic zero also. Right? | |
| May 10, 2016 at 12:06 | answer | added | Vicente Cunha | timeline score: 2 | |
| May 10, 2016 at 12:05 | comment | added | Wouter van Ooijen | It can. In a well-designed circuit the clock cycles are far enough apart with respect to the half-time, so the probability is (very) high. | |
| May 10, 2016 at 11:52 | comment | added | tollin jose | @WoutervanOoijen that means it can settle to either logic zero or logic one at next active clock edge based on half time? | |
| May 10, 2016 at 11:44 | comment | added | Wouter van Ooijen | Metastability has a sort of half-life time. It will fade away towards either 0 or 1. Unfortunately there is no upper limit on the amount of time it will take to do so, but the probability that it will survive for T decays rapidly with T. | |
| May 10, 2016 at 11:40 | history | asked | tollin jose | CC BY-SA 3.0 |