Timeline for Is RAM with read ahead (Look ahead) possible?
Current License: CC BY-SA 3.0
13 events
| when toggle format | what | by | license | comment | |
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| Jul 8, 2016 at 17:47 | vote | accept | CommunityBot | ||
| Jul 4, 2016 at 3:53 | comment | added | Claudio Avi Chami | What you can do, if you access the RAM sequentially, is to register the last data accessed and present it together with the current data accessed. | |
| Jul 4, 2016 at 3:47 | comment | added | Claudio Avi Chami | at the FPGA level you simply can't do that. If you were making an ASIC (maybe) you could access the RAM cells and do the trick. On an FPGA a single-port memory is a defined block where there is a single data bus that reflects the contents of the last requested address. There is no other data bus available, and no LUTs will be able to access data that is not at the RAM port. Any solution to do what you want demand a dual port RAM. | |
| Jul 3, 2016 at 15:52 | comment | added | user105000 | @ClaudioAviChami, I don't want to write to 2 RAMs, I want a single RAM with an extra read port instead of writing to 2 RAMs in parallel. I don't think the complexity of a true dual port RAM or RAM duplication is required since the 2 read addresses are always related in a very specific way. My guess is that FPGAs do not provide native implementations of lookahead RAMs (like AndyW mentioned) and must be implemented using LUTs. | |
| Jul 2, 2016 at 5:04 | comment | added | Claudio Avi Chami | Because you forgot you received a 'simple' solution. A real solution is more complicated because you have to take care of writing to both RAMs. | |
| Jul 1, 2016 at 19:28 | history | edited | user105000 | CC BY-SA 3.0 |
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| Jul 1, 2016 at 19:18 | history | edited | user105000 | CC BY-SA 3.0 |
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| Jul 1, 2016 at 19:01 | history | edited | user105000 | CC BY-SA 3.0 |
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| Jul 1, 2016 at 18:52 | comment | added | user105000 | @ClaudioAviChami, oops! forgot to put a write enable. | |
| Jul 1, 2016 at 18:50 | history | edited | user105000 | CC BY-SA 3.0 |
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| Jul 1, 2016 at 17:26 | answer | added | AndyW | timeline score: 1 | |
| Jul 1, 2016 at 17:12 | comment | added | Claudio Avi Chami | If ISE infers two RAM blocks is because you made an incomplete model of the RAM... how do you thing the second block would be updated when you need to write to the RAM? If BW is the issue, you can burst access the RAM. | |
| Jul 1, 2016 at 16:39 | history | asked | user105000 | CC BY-SA 3.0 |