Timeline for Xilinx Programming FPGA from SPI Flash without JTAG
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 14, 2016 at 22:01 | answer | added | alex.forencich | timeline score: 2 | |
| Aug 14, 2016 at 20:23 | comment | added | Chris Stratton | They call it slave serial: xilinx.com/support/documentation/application_notes/xapp502.pdf Again, this is distinct from the master mode they have which supports some flashes, take time to look at all your options before deciding, though if you already have an MCU in the system letting that do it via slave serial can make a lot of sense, especially as that may be your path for changing the flash contents or want to use part of the flash for something else. | |
| Aug 14, 2016 at 20:18 | comment | added | Ethan | @ChrisStratton Thanks for your comment. I tried looking at the Xilinx documentation and could really only find information on programming the flash memory with the bitstream using JTAG. Can you point me to some useful documentation? Also, I'm not sure what you mean by "send it clock and data." | |
| Aug 14, 2016 at 20:00 | comment | added | Chris Stratton | You really should read the Xilinx literature on this. Some of their FPGAs can act as an SPI master to autonomously read out data from some types of SPI flashes. Failing that, any little micro should be able to read the flash and push the data in via whatever Xilinx calls their "send it clock and data" bitstream interface. | |
| Aug 14, 2016 at 19:58 | review | First posts | |||
| Aug 15, 2016 at 10:45 | |||||
| Aug 14, 2016 at 19:54 | history | asked | Ethan | CC BY-SA 3.0 |