Timeline for Instanciating blocks in VHDL, asignment of clock and reset signals
Current License: CC BY-SA 3.0
3 events
| when toggle format | what | by | license | comment | |
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| Dec 7, 2016 at 22:33 | comment | added | Clone |
Should I usestack0 : stack entity port map(...); if I have stack in the same file? I don't want to specify that component again as it is in the same file.
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| Dec 6, 2016 at 14:36 | vote | accept | Clone | ||
| Dec 6, 2016 at 13:23 | history | answered | A. Kieffer | CC BY-SA 3.0 |