Instanciating blocks in VHDL, asignment of clock and reset signals

Question

I am trying to connect 5 stacks together using VHDL below. The main problem I am facing is that that I don't know how to deal with the signals clk which stands for clock and rst which is asynchronous reset and the SOp stack operation signal-vector which used in its entirety by each of the stack instances. TS stands for top of stack.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity stack is
    port(
        D : in std_logic_vector(4 downto 0);
        TS : out std_logic_vector(4 downto 0);
        clk, rst : in std_logic;
        SOp : in std_logic_vector(1 downto 0)
    );
end entity;

architecture structural of stack is


begin
stack1: entity stack port map(
      D  => D(0),
      TS => Tos(0),
      SOp => -- here
);

stack2: entity stack port map(
      D  => D(1),
      TS => TS(1),
      SOp => -- here
);

stack3: entity stack port map(
      D  => D(2),
      TS => TS(2),
      SOp => -- here
);

stack4: entity stack port map(
      D  => D(3),
      TS => TS(3),
      SOp => -- here
);

stack5: entity stack port map(
      D  => D(4),
      TS => TS(4),
      SOp => -- here
);

end architecture;

Should I basically type something like this or can I just skip SOp, clk, rst as they are used completely by each stack?

stack1: entity stack port map(
      D  => D(0),
      TS => TS(0),
      SOp => SOp,
      clk => clk,
      rst => rst
);

Answer 1

First of all you need to differentiate entities definitions and entities instantiations. What you try to do here is defining an entity and instantiate it in the same file. Your architecture of your entity can't use your entity ...

So I advise you to create a TOP level, that you can call top, stack_top or whatever you want and an entity stack separately.

Your main entity called stack will look like this :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity stack is
     port(
        D : in std_logic;
        TS : out std_logic;
        clk, rst : in std_logic;
        SOp : in std_logic_vector(1 downto 0)
    );
end entity;

architecture structural of stack is


begin

... -- do whatever you need to do

end architecture;

This is you stack function. Now the top level will instantiate as many instances of you stack entity you need.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
     port(
        D : in std_logic_vector(4 downto 0);
        TS : out std_logic_vector(4 downto 0);
        clk, rst : in std_logic;
        SOp : in std_logic_vector(1 downto 0)
    );
end entity;

architecture X of top is

-- call you entity
component stack is
     port(
        D : in std_logic;
        TS : out std_logic;
        clk, rst : in std_logic;
        SOp : in std_logic_vector(1 downto 0)
    );
end component;

begin

-- instantiate your entity
stack0 : stack 
port map  (D => D(0),
           TS => TS(0),
           clk => clk,
           rst => rst,
           SOp => SOp);

stack1 : stack 
port map  (D => D(1),
           TS => TS(1),
           clk => clk,
           rst => rst,
           SOp => SOp);

...

end architecture;

(I assumed that you wanted to map one bit of each of your vector to each stack, that's why I'm using std_logic ports for each stack)