Timeline for Random bit sequence using Verilog
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Apr 24, 2012 at 7:45 | history | edited | clabacchio | CC BY-SA 3.0 |
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| Apr 23, 2012 at 14:17 | history | edited | clabacchio | CC BY-SA 3.0 |
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| Apr 23, 2012 at 11:21 | comment | added | Martin Thompson | @clabacchio: Verilog is only C-like in syntax - it's stilla hardware description language. Building a shift register with XOR feedback is perfectly doable (not being a verilogger, I'll let someone else post the right syntax :) | |
| Apr 23, 2012 at 9:55 | comment | added | clabacchio | @avakar well I don't know Verilog very well, but I think I understood that Verilog was more c-like, while VHDL is closer to the hardware implementation... | |
| Apr 23, 2012 at 9:46 | comment | added | avakar | "Probably this solution is more easily implemented in VHDL", how come? | |
| Apr 23, 2012 at 9:10 | history | answered | clabacchio | CC BY-SA 3.0 |