Timeline for Digital Logic circuit - exam question
Current License: CC BY-SA 3.0
23 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Sep 26, 2017 at 14:24 | comment | added | nrofis | @jalalipop, I did yesterday. Ido Kessler and pasaba por aqui were right, my professor said that the question was wrong and the NAND should be NOR.... | |
| Sep 25, 2017 at 13:37 | comment | added | jalalipop | @nrofis Did you ever get a solution from your professor? I'd be intrigued to see if there was an error in the exam or if we missed something. | |
| Sep 22, 2017 at 13:03 | vote | accept | nrofis | ||
| Sep 21, 2017 at 22:44 | history | tweeted | twitter.com/StackElectronix/status/910998189263736834 | ||
| Sep 21, 2017 at 7:00 | vote | accept | nrofis | ||
| Sep 22, 2017 at 13:03 | |||||
| Sep 21, 2017 at 6:51 | comment | added | nrofis | @Tut, I know Ido, I shared the question with him. I asked him why he deleted his answer and he told me that his answer deleted by mod. His rating is also too low for writing comments.... | |
| Sep 20, 2017 at 10:21 | comment | added | Tut | @nrofis ... How do you know? If his answer was deleted by a mod, I'd like to know why. Presenting a method that is supposed to prove that the problem is unsolvable certainly should be allowed as an answer. | |
| Sep 19, 2017 at 18:27 | comment | added | nrofis | @Tut, he didn't deleted it. Someone else did... | |
| Sep 19, 2017 at 18:19 | answer | added | John | timeline score: -3 | |
| Sep 19, 2017 at 17:02 | answer | added | Agustin Tena | timeline score: 2 | |
| Sep 19, 2017 at 14:43 | comment | added | Tut | @Ido Kessler ... I was intrigued by your solution and if your proof is correct them I'm sorry you deleted it. No one so far seems to have a solution. Perhaps if you included a description of your algorithm, it would improve the answer. How confident are you that it is correct and bug-free? | |
| Sep 19, 2017 at 14:38 | comment | added | pasaba por aqui | @BrianDrummond: if you post a description of the solution you think exists, we could verify it. It is difficult to say that no solution exists, but easy to verify if a solution is valid. | |
| Sep 19, 2017 at 13:56 | answer | added | pasaba por aqui | timeline score: 8 | |
| Sep 19, 2017 at 12:47 | answer | added | Ido Kessler | timeline score: 25 | |
| Sep 19, 2017 at 8:29 | comment | added | nrofis | @BrianDrummond Any idea? Can you solve this? | |
| Sep 18, 2017 at 14:04 | history | edited | Eugene Sh. | CC BY-SA 3.0 |
deleted 16 characters in body; edited title
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| Sep 18, 2017 at 13:31 | comment | added | nrofis | @BrianDrummond My idea was to connect the first,third and forth bits to decoder and to handle the output 0, 2 and 6. The output 0 needs the second bit to be 0 as well, the 2 and 6 need the second bit to be 1. And I didn't succeeded to find a way to check that with the given gates... | |
| Sep 18, 2017 at 13:07 | comment | added | nrofis | @BrianDrummond but I already know that, and I still didn't succeed to solve it. Every solution that I tried feels that it missing one OR gate. I can't found such combination with the given gates that can solve the problem... Note that I have only ONE gate per type... | |
| Sep 18, 2017 at 13:01 | comment | added | user16324 | Good. That description and the list of parts pretty much tells you how to do it. | |
| Sep 18, 2017 at 11:48 | comment | added | nrofis | @BrianDrummond I tried it with every 3 bits. I know that the 3 possible answers are 0000, 0111, 1110. the 2 bits in the center are same - if they are zeros the other two should be zero, and if they are ones, the other two should be 0 and 1... | |
| Sep 18, 2017 at 11:28 | comment | added | user16324 | As a hint : given 4 bits and a 3-8 decoder, you have to treat one of the bits differently. | |
| Sep 18, 2017 at 11:06 | review | First posts | |||
| Sep 18, 2017 at 12:46 | |||||
| Sep 18, 2017 at 11:04 | history | asked | nrofis | CC BY-SA 3.0 |