Timeline for what is the difference between logic,reg and wire in system verilog?? explaination with an example would be helpful
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 22 at 18:32 | answer | added | Harry | timeline score: 1 | |
| Dec 23, 2017 at 9:18 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Nov 22, 2017 at 22:31 | history | bumped | CommunityBot | This question has answers that may be good or bad; the system has marked it active so that they can be reviewed. | |
| Oct 10, 2017 at 3:02 | review | First posts | |||
| Oct 10, 2017 at 8:17 | |||||
| Sep 27, 2017 at 5:42 | answer | added | dave_59 | timeline score: 3 | |
| Sep 27, 2017 at 4:55 | history | asked | Tania Kapoor | CC BY-SA 3.0 |