explanation with an example would be helpful.i tried:- input logic [9:0] data1 as the input of the counter and loaded this value into the count1 (logic [9:0] count;) and then assigned count1<=data1; at the time when load was 1. but it shows some error.


2 Answers 2


There is absolutely no difference between reg and logic in SystemVerilog except for the way they are spelled - they are keyword synonyms. logic is meant to replace reg because reg was originally intended to be short for register. Also note that logic is a data type for a signal, whereas wire is a signal type. Another signal type is a variable.

See this post for a more complete explanation.

  • 1
    \$\begingroup\$ It is totally wrong to say that there is absolutely NO difference between the two. There are many limitations a logic pose. The major difference is that logic will not allow multiple drivers to drive a single variable at the same time and the simulator throws an error. This feature was introduced in SV to ensure that no Write-Write Race takes place. \$\endgroup\$ Commented Mar 17, 2018 at 10:19
  • 3
    \$\begingroup\$ @VidushiBajpai I stand by my answer. Show me a piece of code that works using one type and not with the other \$\endgroup\$
    – dave_59
    Commented Mar 17, 2018 at 21:17
  • 1
    \$\begingroup\$ @dave_59 There is a lexical restriction on the reg keyword, see §6.7.1 LRM 1800-2017. A net type keyword directly followed by reg keyword is not allowed. E.g. wire reg is not allowed, tri reg is not allowed, ... \$\endgroup\$
    – HKOB
    Commented Sep 12, 2018 at 4:15

@dave_59's answer is correct, but for a relative SV newbie like me, it left some questions unanswered. Judging by the comments beneath @dave_59's answer, I was not alone.

1. A helpful white paper

This confusing topic (and its remarkably convoluted history) was clarified really well in this white paper: "Logic vs Wire in SV – some misconceptions", Mitu Raj, 2024. The author personally credits @dave_59 as the "living LRM" for correcting misconceptions about this topic all over the internet.

To paraphrase that white paper:

  • In SystemVerilog 3.1 (2004), logic, reg and wire were all considered to be data types.
    • logic was an unresolved data type, meaning multiple drivers were forbidden.
  • In SystemVerilog-2017 (IEEE Std 1800-2017), a new distinction was made between data types and data objects.
    • Data objects are divided into variables and nets.
      • Variable type data objects are declared using the optional keyword var.
      • Net type data objects are declared using a net type keyword (wire, wand, wor, etc).
    • All data objects (variables and nets) have a data type.
    • logic is a data type.
    • Therefore, both variables and nets can have type logic.
wire logic [3:0] data_0;  // data_0 is a net of type logic
var  logic [3:0] data_1;  // data_1 is a variable of type logic

So, we can answer the comment from @VidushiBajpai:

It is no longer true to say that logic is an unresolved data type. Since SystemVerilog-2017, it depends on the data object. Net type data objects (including those of data type logic) are resolved according to the resolution function of the net type (or unresolved in the case of uwire). Variables (including those of data type logic) cannot have multiple drivers (in VHDL terminology, they are unresolved).

2. logic and reg denote the same type

I checked the LRM (IEEE Std 1800-2017) and §6.11.2 confirms @dave_59's answer:

logic and reg denote the same type

Some more detail from §6.11:

enter image description here

3. Lexical restriction on reg

Regarding the comment by @HKOB, I see the same in the LRM (IEEE Std 1800-2017):

A net type keyword shall not be followed directly by the reg keyword.


The reg keyword can be used in a net or port declaration if there are lexical elements between the net type keyword and the reg keyword.

I'm not sure why this restriction exists.


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