please find my RTL code below

module shifter #(parameter Length = 1) (

input clk, input rst, input EN, input WR, input RD, input SI, output reg SO, inout [Length-1:0] Data
);

reg [Length-1:0] register;

always@(posedge clk or posedge rst) begin if(rst == 1'b1) begin register <= 0; end else
begin if(WR == 1'b1 && EN == 1'b0) begin register <= Data; end

 else if(WR == 1'b0 && EN == 1'b1)
         begin
     register <= {SI, register[Length-1:1]};           
         SO <= register [0];
     end     
      
   
  else if(WR == 1'b1 && EN == 1'b1)
       begin
       $display ("Illegal state");         
       end 
       
 else
     begin
     register <= register;
     end             
    
  end  
   end

assign Data = (RD == 1'b1) ? register [Length-1:0] : {(Length){1'bz}};

endmodule

module shifter #(parameter Length = 1) (

  input clk,
  input rst,
  input EN,
  input WR,
  input RD,
  input SI,
  output reg SO,
  inout [Length-1:0] Data  
  );
  
  reg [Length-1:0] register;      
   
  always@(posedge clk or posedge rst)
  begin
    if(rst == 1'b1)
       begin
        register <= 0;
       end
    else      
     begin
         if(WR == 1'b1 && EN == 1'b0)
        begin
          register <= Data;
        end
         
     else if(WR == 1'b0 && EN == 1'b1)
             begin
         register <= {SI, register[Length-1:1]};           
             SO <= register [0];
         end                 
       
      else if(WR == 1'b1 && EN == 1'b1)
           begin
           $display ("Illegal state");         
           end 
           
     else
         begin
         register <= register;
         end             
        
      end  
       end
        
   assign Data = (RD == 1'b1) ? register [Length-1:0] : {(Length){1'bz}};
   
   endmodule