Timeline for Differential gain on BJT differential pair: not symmetric?
Current License: CC BY-SA 4.0
20 events
| when toggle format | what | by | license | comment | |
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| Jun 4, 2018 at 6:00 | comment | added | jonk | @WatsonHolmes Yes. It is, I believe. Do you want to know how to set this up properly in LTspice? | |
| Jun 3, 2018 at 14:21 | comment | added | WatsonHolmes | @john Yes of course, they're not in series so they shouldn't have the same current. I did an AC Sweep making VD with 1V of amplitude and the traced V(vo1) and V(vo2). Maybe it is how I connected Vc and Vd. | |
| Jun 3, 2018 at 9:15 | answer | added | LvW | timeline score: 1 | |
| Jun 3, 2018 at 7:03 | comment | added | Avid Pro Tool | @WatsonHolmes What would happen if you tried the two V_D/2 sources and took your measurements again? I don't know enough about exactly what you're doing to give you a definitive answer. | |
| Jun 3, 2018 at 6:55 | comment | added | jonk | @WatsonHolmes The (+) and (-) power supplies should NOT have the same currents, though. Do you see why? You should. | |
| Jun 3, 2018 at 6:53 | comment | added | jonk | @WatsonHolmes CA3096, if it were to be fixed with a proper PNP, would be my darling part. As it is, I get stuck using MC1496 for things it was never intended to be. Oh, well. I still don't know HOW you measured the gains to demonstrate they are different. I suspect it is your crazy VC/VD arrangement misused. But who knows? Can you discuss how you made your measurements of gain? | |
| Jun 3, 2018 at 6:53 | comment | added | WatsonHolmes | @AvidProTool is it? I read on Sedra and Smith a few hours ago that those 2 ways of connecting the sources are slightly different but they don't go further on the subject (they say it's not relevant on the context). | |
| Jun 3, 2018 at 6:51 | comment | added | WatsonHolmes | @jonk I was just guessing, I'm trying to figure out what can be different that can justify the non symmetric gains [I also forgot to add in the last answer, it's interesting that you point out that about CA3046 since all the integrated circuits on the lab are CA3046] | |
| Jun 3, 2018 at 6:49 | comment | added | Avid Pro Tool | Isn't that unbalanced operation though as opposed to fully differential and impedance balanced? The bases of each transistor don't see the same source impedance since one is shorted to ground. There is no symmetry at the inputs. | |
| Jun 3, 2018 at 6:47 | comment | added | jonk | @WatsonHolmes Also, did you mention gains were different? How did you test this, in particular? (The currents in the supplies should be different, so I don't care much about that problem.) | |
| Jun 3, 2018 at 6:42 | comment | added | WatsonHolmes | @AvidProTool when I'm simulating AC analysis or Transient with the VD source I ground the VC source so Q4 is grounded and Q3 is connected to VD which is the same thing as having VD/2 connected to Q3 and -VD/2 connected to Q4. | |
| Jun 3, 2018 at 6:41 | comment | added | jonk | @WatsonHolmes Why shouldn't they be different? | |
| Jun 3, 2018 at 6:40 | comment | added | WatsonHolmes | @jonk I was comparing I(Vee) and I(Vcc). They are different but should they? | |
| Jun 3, 2018 at 6:27 | comment | added | Avid Pro Tool | I'm curious about what you're doing there with VC and why you aren't feeding each input of the differential pair with its own ground referenced V_D/2 source? | |
| Jun 3, 2018 at 6:21 | comment | added | jonk | Which specific numbers are you comparing and finding different. You list all of them. Provide a focus for me. [Sidebar: CA3046 is getting hard to find these days. My favorite the CA3096 (which should have the PNP's improved, damn them) is even harder, I suppose.] | |
| Jun 3, 2018 at 6:16 | comment | added | WatsonHolmes | Hi! Thanks for the quick answer. I edited the question to provide a little bit more information. | |
| Jun 3, 2018 at 6:15 | history | edited | WatsonHolmes | CC BY-SA 4.0 |
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| Jun 3, 2018 at 5:57 | comment | added | jonk | Provide a schematic (yes, of course, we all know what a BJT diff-pair, or a long-tailed pair, is.) But I'd rather not assume anything. I'd also like to see your development because that shows me where your questions really lay. You suggest symmetry, but I honestly have no idea how you TESTED this. And I'd like to see how you did. Show me. (You say you did this in LTspice, so it should be easy to include the netlist from it, for example.) | |
| Jun 3, 2018 at 5:53 | review | First posts | |||
| Jun 3, 2018 at 6:27 | |||||
| Jun 3, 2018 at 5:50 | history | asked | WatsonHolmes | CC BY-SA 4.0 |