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D.A.S.
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How do you decide the best choice?

Define your acceptance criteriaDefine your acceptance criteria based on Vin-out Static Tolerance and Step load error at a minimum with test results using your worst specs. 

Then test in a representative PCB layout and verify and record margins at worst case temp for your environment and worst case step and preloads. 0 preload is worst. Cap ESR is a critical tradeoff between step load error and phase margin.

Static source impedance and step load impedance are different thus static load regulation and step load errors are different. Phase margin depends on source and load caps and step loads.

Careful selection and layout matched to your needs may lead to success or failure depending on your specs.

If you don't recognize the differences below or that some do not specify stability margins, then consult with someone who does or read more about phase margin and ask a better question.

PN       Vout tol. Imax  Typ Load Reg. @0.8A  Zo  Vin-out [email protected] Cout
======= ==== ====  ===    ====               ======  ============  ====
AMS1117 3.3V 1.5%  1A     3 mV     3mV/0.8A= 3.75mΩ  1.1V          22µF solid tant.
NCP1117 3.3V 1%    1.5A   4.3 mV  4.3m/0.8A= 5.38mΩ  1.07V     80mV typ 0.1 to 0.5A step @ 10uF

calc...NCP1117 80mV/500mA = 160 mΩ  80mV= = +/-2% error from 400mA steps with 100mA preload  

NCP Instability points

1A step load CESR= 50uF1mΩ=50ns, 20uF10mΩ=200ns, 2uF80mΩ=160ns, 1uF*200mΩ=200ns
Static Load >20mΩ 10uF ceramic input , 10uF Tantalum output

How do you decide the best choice?

Define your acceptance criteria based on Vin-out Static Tolerance and Step load error at a minimum with test results using your worst specs. Then test in a representative PCB layout and verify and record margins at worst case temp for your environment and worst case step and preloads. 0 preload is worst.

If you don't recognize the differences below or that some do not specify stability margins, then consult with someone who does or read more about phase margin and ask a better question.

PN       Vout tol. Imax  Typ Load Reg. @0.8A  Zo  Vin-out [email protected] Cout
======= ==== ====  ===    ====               ======  ============  ====
AMS1117 3.3V 1.5%  1A     3 mV     3mV/0.8A= 3.75mΩ  1.1V          22µF solid tant.
NCP1117 3.3V 1%    1.5A   4.3 mV  4.3m/0.8A= 5.38mΩ  1.07V     80mV typ 0.1 to 0.5A step @ 10uF

calc...NCP1117 80mV/500mA = 160 mΩ  80mV= = +/-2% error from 400mA steps with 100mA preload  

NCP Instability points

1A step load CESR= 50uF1mΩ=50ns, 20uF10mΩ=200ns, 2uF80mΩ=160ns, 1uF*200mΩ=200ns
Static Load >20mΩ 10uF ceramic input , 10uF Tantalum output

How do you decide the best choice?

Define your acceptance criteria based on Vin-out Static Tolerance and Step load error at a minimum with test results using your worst specs. 

Then test in a representative PCB layout and verify and record margins at worst case temp for your environment and worst case step and preloads. 0 preload is worst. Cap ESR is a critical tradeoff between step load error and phase margin.

Static source impedance and step load impedance are different thus static load regulation and step load errors are different. Phase margin depends on source and load caps and step loads.

Careful selection and layout matched to your needs may lead to success or failure depending on your specs.

If you don't recognize the differences below or that some do not specify stability margins, then consult with someone who does or read more about phase margin and ask a better question.

PN       Vout tol. Imax  Typ Load Reg. @0.8A  Zo  Vin-out [email protected] Cout
======= ==== ====  ===    ====               ======  ============  ====
AMS1117 3.3V 1.5%  1A     3 mV     3mV/0.8A= 3.75mΩ  1.1V          22µF solid tant.
NCP1117 3.3V 1%    1.5A   4.3 mV  4.3m/0.8A= 5.38mΩ  1.07V     80mV typ 0.1 to 0.5A step @ 10uF

calc...NCP1117 80mV/500mA = 160 mΩ  80mV= = +/-2% error from 400mA steps with 100mA preload  

NCP Instability points

1A step load CESR= 50uF1mΩ=50ns, 20uF10mΩ=200ns, 2uF80mΩ=160ns, 1uF*200mΩ=200ns
Static Load >20mΩ 10uF ceramic input , 10uF Tantalum output

Source Link
D.A.S.
  • 148k
  • 3
  • 56
  • 190

How do you decide the best choice?

Define your acceptance criteria based on Vin-out Static Tolerance and Step load error at a minimum with test results using your worst specs. Then test in a representative PCB layout and verify and record margins at worst case temp for your environment and worst case step and preloads. 0 preload is worst.

If you don't recognize the differences below or that some do not specify stability margins, then consult with someone who does or read more about phase margin and ask a better question.

PN       Vout tol. Imax  Typ Load Reg. @0.8A  Zo  Vin-out [email protected] Cout
======= ==== ====  ===    ====               ======  ============  ====
AMS1117 3.3V 1.5%  1A     3 mV     3mV/0.8A= 3.75mΩ  1.1V          22µF solid tant.
NCP1117 3.3V 1%    1.5A   4.3 mV  4.3m/0.8A= 5.38mΩ  1.07V     80mV typ 0.1 to 0.5A step @ 10uF

calc...NCP1117 80mV/500mA = 160 mΩ  80mV= = +/-2% error from 400mA steps with 100mA preload  

NCP Instability points

1A step load CESR= 50uF1mΩ=50ns, 20uF10mΩ=200ns, 2uF80mΩ=160ns, 1uF*200mΩ=200ns
Static Load >20mΩ 10uF ceramic input , 10uF Tantalum output