Timeline for Why propagation delay is measured at 50% of the input and output waveform?
Current License: CC BY-SA 4.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jun 2, 2019 at 12:15 | comment | added | Janka | Correct. That's why I wrote the schematic is misleading. C1 is connected symetrically, regardless if it's bound to GND or Vdd. | |
| Jun 2, 2019 at 12:11 | comment | added | Elliot Alderson | @Janka It doesn't matter where the capacitor is connected (as long as it is a fixed voltage), it looks the same to the inverter output. | |
| Jun 2, 2019 at 9:56 | vote | accept | Naman Yadav | ||
| Jun 2, 2019 at 9:56 | |||||
| Jun 2, 2019 at 7:53 | comment | added | Rajesh Shashi Kumar | The schematic was only to roughly illustrate the point of calculating propagation delays and the input/output transitions. | |
| Jun 2, 2019 at 7:43 | comment | added | Janka | The schematic is a bit misleading as it only shows a cap to GND. For high frequencies, GND and Vdd are essentially the same. The cap should either go to Vdd/2 or there should be two caps. | |
| Jun 2, 2019 at 7:33 | history | answered | Rajesh Shashi Kumar | CC BY-SA 4.0 |