Timeline for Direct coupling Biasing of Two stage amp
Current License: CC BY-SA 4.0
12 events
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Jun 17, 2019 at 17:09 | vote | accept | Char | ||
Jun 17, 2019 at 16:48 | comment | added | Char | @ThePhoton It is a design. What is confusing is aren't M8 and M7 effectively two current sources fighting each other? In that case if the currents are skewed in either direction the output common mode skews as well. So in a nominal case you can find the right W/L ratio to get it to be relatively balanced. But over PVT you cannot guarantee that and so either the pmos or nmos maybe stronger and thus your output common mode forces one of the devices in triode? | |
Jun 17, 2019 at 16:44 | answer | added | Bimpelrekkie | timeline score: 2 | |
Jun 17, 2019 at 16:42 | comment | added | The Photon | Are you asking this as part of doing a homework problem or design project? If you increase Vdd-Vss you would not run into this problem. But maybe you were asked to design for a fairly low supply voltage as a challenge? | |
Jun 17, 2019 at 16:41 | history | edited | Char | CC BY-SA 4.0 |
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Jun 17, 2019 at 16:32 | comment | added | Char | @ThePhoton Added an img. I'm referring to M8 and M7. Thanks | |
Jun 17, 2019 at 16:31 | comment | added | Char | @glen_geek I agree, but in an amp isn't it desirable to have both devices in sat? I don't think the intent is to yank the load in this case? | |
Jun 17, 2019 at 16:28 | history | edited | Char | CC BY-SA 4.0 |
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Jun 17, 2019 at 16:24 | comment | added | glen_geek | I see it as having lots of current available to yank a load up or down. That also makes rise time and fall time similar. | |
Jun 17, 2019 at 16:22 | comment | added | The Photon | Can you include a schematic of the circuit you're asking about. I probably understand what you are talking about, but details matter. | |
Jun 17, 2019 at 16:10 | review | First posts | |||
Jun 17, 2019 at 16:25 | |||||
Jun 17, 2019 at 16:07 | history | asked | Char | CC BY-SA 4.0 |