Timeline for 100s of devices on SPI bus with daisy chaining - theoretically possible but who's done it?
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
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| Jul 24, 2019 at 17:00 | comment | added | josh | I'll look into the 74AC244 and 74AC125. Did you need to take account of any delay in the buffer if clock is buffered and the CS and MOSI are not? | |
| Jul 23, 2019 at 16:35 | vote | accept | josh | ||
| Jul 23, 2019 at 13:47 | comment | added | CrossRoads | Then you could have 4 arrays per string, with each array supporting channel 1, 2, 3, or 4 of each chip. If a channel changes, update that array and blast the data out. I've daisy chained 45 shift registers with a single MOSI, with similar buffering, using 74AC125 and 5 strings of 9 shift registers, clocking data in at 8 MHZ SPI rate. Each string of 9 was on it's own board with a SCSI connector to bring out 3 Gnds and 65 outputs out to the user. (7 bits of last shift register were not used). You need to consider how the 3 pins/output will be connected to whatever follows. | |
| Jul 23, 2019 at 13:38 | comment | added | CrossRoads | You need 11 bits/channel, so having 8 or 16 chips per string would use all 88 bits of an 11 byte SPI burst, or all 176 bits of a 22 byte burst of data. With AD5204, 16 chip strings gives 64 channels, 8 strings gives 512 channels. I would buffer SCK and chip select to each string with a 74AC244 each (so that SCK and CS see 8 loads, and then each AC244 output sees 8 or 16 loads that are more distributed). MOSI can be buffered also, but it only goes to the 1st chip in each string, so it may not need it. Only 1 more chip to wire up, so it wouldn't hurt to add it. 512 knobs/128 pots? Clarify. | |
| Jul 23, 2019 at 12:28 | answer | added | Kripacharys | timeline score: 5 | |
| Jul 23, 2019 at 11:15 | comment | added | Peter Smith | The output resistance of the ATMega appears to be of the order of 130 ohms. The input capacitance of each device is 7pF (typical) for a load of 241 pF (32 devices). Track capacitance is about 1.1pF / inch for a 4 thou track over a return path with 4 thou between the return and track. I would expect the clock signal (at the very least) to need buffering. The total delay through the chain is likely to limit the data rate to lower than your target (the actual delay through each device is load dependent). | |
| Jul 23, 2019 at 10:53 | comment | added | josh | SPI clocked in at 250 kHz, I corrected my opps on the number of pots vs number devices. | |
| Jul 23, 2019 at 10:51 | history | edited | josh | CC BY-SA 4.0 |
added 4 characters in body
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| Jul 23, 2019 at 10:43 | comment | added | Dave Tweed | You're missing the fact that each AD5204 controls 4 "knobs", so you only need a total of 32 devices. In any case, the clock line goes to every chip, so it'll probably need a buffer. | |
| Jul 23, 2019 at 10:23 | comment | added | winny | How fast are you clocking date via SPI? | |
| Jul 23, 2019 at 10:14 | history | asked | josh | CC BY-SA 4.0 |