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I need to control 512 knobs digitally using 128 digital potentiometers. The AD5204 supports daisy-chaining but what do I need to be careful of when interfacing this with a ATmega328P?

I plan to split this across 8 chip select lines with 16 devices on each chip select (CS) line. It looks like the digital out is powered by the device so to me it looks like it will work.

What am I missing?

  • Will the atMega drive so many devices, if not how should I amplify the bus?
  • The CS will be held low for a command of 176 bit for the commands to get to the last in the chain.
  • Noise considerations - erm, low pass filters and load resisters?
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  • \$\begingroup\$ How fast are you clocking date via SPI? \$\endgroup\$ – winny Jul 23 at 10:23
  • \$\begingroup\$ You're missing the fact that each AD5204 controls 4 "knobs", so you only need a total of 32 devices. In any case, the clock line goes to every chip, so it'll probably need a buffer. \$\endgroup\$ – Dave Tweed Jul 23 at 10:43
  • \$\begingroup\$ SPI clocked in at 250 kHz, I corrected my opps on the number of pots vs number devices. \$\endgroup\$ – josh Jul 23 at 10:53
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    \$\begingroup\$ The output resistance of the ATMega appears to be of the order of 130 ohms. The input capacitance of each device is 7pF (typical) for a load of 241 pF (32 devices). Track capacitance is about 1.1pF / inch for a 4 thou track over a return path with 4 thou between the return and track. I would expect the clock signal (at the very least) to need buffering. The total delay through the chain is likely to limit the data rate to lower than your target (the actual delay through each device is load dependent). \$\endgroup\$ – Peter Smith Jul 23 at 11:15
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    \$\begingroup\$ You need 11 bits/channel, so having 8 or 16 chips per string would use all 88 bits of an 11 byte SPI burst, or all 176 bits of a 22 byte burst of data. With AD5204, 16 chip strings gives 64 channels, 8 strings gives 512 channels. I would buffer SCK and chip select to each string with a 74AC244 each (so that SCK and CS see 8 loads, and then each AC244 output sees 8 or 16 loads that are more distributed). MOSI can be buffered also, but it only goes to the 1st chip in each string, so it may not need it. Only 1 more chip to wire up, so it wouldn't hurt to add it. 512 knobs/128 pots? Clarify. \$\endgroup\$ – CrossRoads Jul 23 at 13:38
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I think you're good to go. A few points I noticed tho'...

  1. your SDO requires a pullup. So clock speed needs adjustment accordingly (see datasheet)
  2. the 'mega SDO will be driving 8x chips, but I think it should be ok.
  3. use standard best practices in terms of PS decoupling and layout.
  4. datasheet mentions SPI 'compatible'. I could not quickly find where the differences are, other than non-8 bit codes. But since you are daisy chaining 16,it shouldn't be a problem.
  5. Max speeds will depend on your trace lengths, so derate speeds accordingly.
  6. You'll have to ENSURE exact number of bits/ clocks, otherwise your chain could get seriously messed up !

Cheers

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  • \$\begingroup\$ Each SDO only drives a single SDI (that's the definition of daisy chain in this context) \$\endgroup\$ – Peter Smith Jul 23 at 12:43
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    \$\begingroup\$ @PeterSmith what do you mean? The proposed design has 8 parallel daisy chains of 16 devices each. So the mega SDO will be connected to 8 chips SDI \$\endgroup\$ – Kripacharya Jul 23 at 13:21
  • \$\begingroup\$ The data path is serial (daisy chained) with each SDO going to the next SDI. See ti.com/lit/an/slvae25/slvae25.pdf \$\endgroup\$ – Peter Smith Jul 23 at 14:09
  • \$\begingroup\$ Yes I know what daisy chain is. Perhaps you have not understood the proposed design. There are 8 daisy chains of 16 devices each, in parallel. The first in each of the 8 chains will be connected to the single SDO pin of the ATMEGA. The devices themselves will of course connect SDO--SDI one on one. I was referring to only the FIRST AD5204 of each chain. I cannot explain it further without your paying closer attention to whats been written. \$\endgroup\$ – Kripacharya Jul 23 at 14:15

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