Timeline for Verifying custom Qsys component?
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
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| Jul 24, 2019 at 6:49 | comment | added | DonFusili | Do you script your synthesis runs? | |
| Jul 24, 2019 at 6:35 | comment | added | gyuunyuu | DonFusili, this is when debugging my own RTL to verify that it does the right things in the Qsys system. This basically involves verifying that the Avalon-MM interfaces correctly latch input and write output. | |
| S Jul 23, 2019 at 16:41 | history | edited | jusaca | CC BY-SA 4.0 |
improved formatting and corrected spelling.
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| S Jul 23, 2019 at 16:41 | history | suggested | CmYang | CC BY-SA 4.0 |
improved formatting and corrected spelling.
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| Jul 23, 2019 at 16:38 | answer | added | Tom Carpenter | timeline score: 1 | |
| Jul 23, 2019 at 16:36 | comment | added | Tom Carpenter | Just edit the file in the simulation folder and then copy it back to your IP directory when done. | |
| Jul 23, 2019 at 16:18 | comment | added | DonFusili | Is this when you are debugging your own RTL that interfaces with the QSys blocks or when you are debugging the generated QSys blocks to see if you got the parameters correctly? | |
| Jul 23, 2019 at 16:17 | review | Suggested edits | |||
| S Jul 23, 2019 at 16:41 | |||||
| Jul 23, 2019 at 15:13 | history | asked | gyuunyuu | CC BY-SA 4.0 |