Timeline for PISO buffer for the MachXO2
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Sep 14, 2019 at 12:17 | vote | accept | Cal-linux | ||
| Sep 13, 2019 at 15:49 | comment | added | Oldfart | It can be done using block rams (as Dave Tweed shows below) but I strongly suspect you have an XY problem. Especially as you say "your microprocessor can always read the samples from the FPGA sequentially". | |
| Sep 13, 2019 at 15:40 | comment | added | Cal-linux | @DaveTweed -- yes, with RAM. My comment was that a pure HDL solution does not work, because we have no more than 7 thousand LUTs. And with RAM, the issue is that I'm not finding a PISO structure available as an IP (free or otherwise) | |
| Sep 13, 2019 at 15:40 | answer | added | Dave Tweed | timeline score: 1 | |
| Sep 13, 2019 at 15:38 | history | edited | Cal-linux | CC BY-SA 4.0 |
added 311 characters in body
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| Sep 13, 2019 at 15:28 | comment | added | Cal-linux | @Oldfart -- I'll adjust my post to clarify this. | |
| Sep 13, 2019 at 15:28 | comment | added | Dave Tweed | How big a buffer do you need? The XO2-7000 has almost 240 kbits of RAM in 26 blocks, which would allow you to double-buffer about 13 kB of data with no problem. | |
| Sep 13, 2019 at 15:24 | comment | added | Oldfart | You do not tell us how big your 'double buffer' is. A double buffer in a UART requires 8 bits. For an ADC (lets say 16 bits) that would be 16 bits The XO2-7000 has >6800 LUTS. I suspect your idea of a 'double buffer' might be slightly out of kilter. | |
| Sep 13, 2019 at 14:48 | history | asked | Cal-linux | CC BY-SA 4.0 |