I had quite a bit of success using LTSpice to build a multiplexer with essentially two transistors. The example I'm attaching, "Mx4_Prob.asc", uses three MOSFETs, the two mentioned and one to amplify the voltage back up to five volts. Then I built a schematic to store one bit of data by connecting the amplified output of the multiplexer back into one of the data inputs of the multiplexer. It appeared to work just fine until I got to the point where the control bit stayed low, but the data input bit went high. I'm attaching "Problem_b.asc" which illustrates the problem. The multiplexer has three inputs, one control bit, (ContWire), and two data bits, (LowWire) and (HighWire). And its single output bit is (Amped). The schematic for bit storage has two inputs, one control bit, (Shift), and one data bit, (DataIn). Its single output bit is (DataOut). Drawing an equivalence between the two schematics, (Shift) plays the part of (ContWire), and (DataIn) plays the part of (HighWire). The part of (LowWire) is played by the output of the amplified output wired back in to the input of MOSFET (Keep0). It seems like the same thing should happen for both schematics, but it's not. As soon as (DataIn) goes high, the output goes high, even though (Shift) stays low. Can anyone tell me why it's behaving this way? I need the output to stay low until (Shift) goes high.

I had quite a bit of success using LTSpice to build a multiplexer with essentially two transistors. The example I'm attaching, "Mx4_Prob.asc", uses three MOSFETs, the two mentioned and one to amplify the voltage back up to five volts. 

Then I built a schematic to store one bit of data by connecting the amplified output of the multiplexer back into one of the data inputs of the multiplexer. It appeared to work just fine until I got to the point where the control bit stayed low, but the data input bit went high. I'm attaching "Problem_b.asc" which illustrates the problem. 

The multiplexer has three inputs, one control bit, (ContWire), and two data bits, (LowWire) and (HighWire). And its single output bit is (Amped). The schematic for bit storage has two inputs, one control bit, (Shift), and one data bit, (DataIn). Its single output bit is (DataOut). Drawing an equivalence between the two schematics, (Shift) plays the part of (ContWire), and (DataIn) plays the part of (HighWire). The part of (LowWire) is played by the output of the amplified output wired back in to the input of MOSFET (Keep0). 

It seems like the same thing should happen for both schematics, but it's not. As soon as (DataIn) goes high, the output goes high, even though (Shift) stays low. Can anyone tell me why it's behaving this way? I need the output to stay low until (Shift) goes high.

Version 4
SHEET 1 1272 680
WIRE 384 -32 -992 -32
WIRE -992 16 -992 -32
WIRE 1216 144 880 144
WIRE 480 160 -992 160
WIRE 480 176 480 160
WIRE -992 192 -992 160
WIRE 880 192 880 144
WIRE 1216 192 1216 144
WIRE 384 256 384 -32
WIRE 432 256 384 256
WIRE 704 272 480 272
WIRE 480 320 -992 320
WIRE 880 336 880 272
WIRE 480 352 480 320
WIRE 1216 352 1216 272
WIRE -992 368 -992 320
WIRE 880 368 880 336
WIRE 384 432 384 256
WIRE 432 432 384 432
WIRE 704 448 704 272
WIRE 704 448 480 448
WIRE 768 448 704 448
WIRE 832 448 768 448
WIRE 880 544 880 464
FLAG 384 -32 ContWire
FLAG 480 160 LowWire
FLAG 480 320 HighWire
FLAG -992 448 0
FLAG -992 272 0
FLAG -992 96 0
FLAG 880 544 0
FLAG 1216 352 0
FLAG 768 448 Ampee
FLAG 880 336 Amped
SYMBOL voltage -992 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Control
SYMATTR Value PWL(0n 0.05 9.5n 0.05 10n 4.95 14.5n 4.95)
SYMBOL voltage -992 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName LowValue
SYMATTR Value PWL(0n 0 14.5n 0)
SYMBOL voltage -992 352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName HighValue
SYMATTR Value PWL(0n 0.1 4.5n 0.1 5n 5 14.5n 5)
SYMBOL pmos4 432 176 R0
SYMATTR InstName PassLow
SYMBOL nmos4 432 352 R0
SYMATTR InstName PassHigh
SYMBOL pmos4 832 368 R0
SYMATTR InstName Amp
SYMBOL voltage 1216 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 864 176 R0
SYMATTR InstName Inverter
SYMATTR Value 100000000
TEXT -1024 552 Left 2 !.tran 0 40n 0n 0.5n

Version 4
SHEET 1 1272 1712
WIRE -912 496 -1008 496
WIRE -912 544 -912 496
WIRE -912 688 -912 624
WIRE -480 688 -624 688
WIRE -480 736 -480 688
WIRE -480 864 -480 816
WIRE -1008 880 -1008 496
WIRE -880 880 -1008 880
WIRE -880 928 -880 880
WIRE -624 944 -624 688
WIRE -928 1008 -1024 1008
WIRE -752 1024 -880 1024
WIRE -624 1104 -624 1024
WIRE -624 1104 -880 1104
WIRE -880 1168 -880 1104
WIRE -624 1168 -624 1104
WIRE -1024 1248 -1024 1008
WIRE -928 1248 -1024 1248
WIRE -752 1248 -752 1024
WIRE -672 1248 -752 1248
WIRE -880 1312 -880 1264
WIRE -752 1312 -752 1248
WIRE -752 1312 -880 1312
WIRE -624 1424 -624 1264
WIRE -1024 1440 -1024 1248
WIRE -1024 1600 -1024 1520
FLAG -624 1424 0
FLAG -912 688 0
FLAG -1024 1600 0
FLAG -480 864 0
FLAG -1008 880 DataIn
FLAG -1024 1248 Shift
FLAG -624 1104 DataOut
SYMBOL voltage -912 528 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName SupplyDataIn
SYMATTR Value PWL(0p 0 19p 0 20p 4.95 39p 4.95)
SYMBOL nmos4 -928 928 R0
SYMATTR InstName Shift0
SYMBOL pmos4 -928 1168 R0
SYMATTR InstName Keep0
SYMBOL pmos4 -672 1168 R0
SYMATTR InstName Amp0
SYMBOL res -640 928 R0
SYMATTR InstName Invert0
SYMATTR Value 1000000000
SYMBOL voltage -480 720 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vHigh
SYMATTR Value 5
SYMBOL voltage -1024 1424 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName SupplyShift
SYMATTR Value PWL(0p 5 9p 5 10p 0.05 29p 0.05 30p 5 39p 5)
TEXT -1064 1640 Left 2 !.tran 0 39p 0p .05p
TEXT -968 1688 Top 1 ;(C) Kevin Simonson 2020