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May 1, 2020 at 15:13 comment added Fredled @crj11 That's a solution to explore, on top of the other answers. The biggest problem it seems, is the delay it takes to stabilize the pulse between each enable/disable cycle.
May 1, 2020 at 7:08 answer added user173271 timeline score: 2
May 1, 2020 at 0:36 answer added Bruce Abbott timeline score: 2
May 1, 2020 at 0:30 comment added dsgdfg Why don't check your smart phone mainboard for solution. So you will be see more analog switching ic's. And you can't divide frequency like this, got stability problems. Use an FPGA or CPLD, maybe you can success but never create an feedbak point !
May 1, 2020 at 0:02 comment added crj11 If you're running at 3.3V, you might be able to use a low threshold PFET like the NX3008PBKW to turn off the connection between X2 and R1/Rbias. You would also have to add a resistor of the same order as Rbias to pull the X1 input to ground when the PFET gate was at 3.3V.
Apr 30, 2020 at 23:28 comment added glen_geek Perturbing this Xtal oscillator may be a bad idea...crystals are high-Q which means that their oscillating amplitude changes slowly with time. It takes many, many cycles to stabilize.
Apr 30, 2020 at 22:54 comment added David Could you instead disconnect the output from the next stage, perhaps using a small FET? Effectively this turns off the clock signal from the view of any downstream components. It also has the benefit that your clock source remains stable.
Apr 30, 2020 at 21:58 history edited Fredled CC BY-SA 4.0
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Apr 30, 2020 at 21:51 history asked Fredled CC BY-SA 4.0