Timeline for Is STM32 RTC halted during debug or not?
Current License: CC BY-SA 4.0
11 events
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May 15, 2020 at 10:53 | vote | accept | Welgriv | ||
May 11, 2020 at 15:34 | history | edited | JRE | CC BY-SA 4.0 |
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May 11, 2020 at 14:44 | history | edited | Welgriv | CC BY-SA 4.0 |
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May 11, 2020 at 12:40 | history | edited | Welgriv | CC BY-SA 4.0 |
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May 11, 2020 at 12:39 | answer | added | Welgriv | timeline score: 3 | |
May 11, 2020 at 12:29 | comment | added | Welgriv | If you read carefully my question you'll see that I note and I know that: IWDG and WWDG also have their "own" clock source and can explicitly be altered during debug. Debug does not act only on the CPU since outside-CPU-timers on APB bus can also be altered during debug. (Btw, LSI RC clock can be selected as the RTC clock source and is not generated by a crystal. It is on the chip and probably a basic oscillator) | |
May 11, 2020 at 11:38 | comment | added | brhans | The answer to that is a definite 'yes'. Stopping the CPU has no effect at all on the RTC's counter - it continues to count since it has it's own dedicated clock source (the 32kHz crystal). | |
May 11, 2020 at 11:34 | comment | added | Welgriv | My problem is if I break at some point will the RTC still count ? I think the answer is yes but I would like a reliable source for this. | |
May 11, 2020 at 11:31 | comment | added | brhans | I'm currently developing on a STM32F427 and on this device I haven't observed any effect on the RTC when debugging. It's clocked by its own separate crystal and powered by its own battery, and the config settings are kept 'safe' behind an unlocking sequence. Enabling/disabling the peripheral clock to the RTC module has no effect on the RTC's counter or anything else in the domain powered by the RTC battery and clocked by the RTC crystal. | |
May 11, 2020 at 11:19 | review | First posts | |||
May 19, 2020 at 9:22 | |||||
May 11, 2020 at 11:15 | history | asked | Welgriv | CC BY-SA 4.0 |