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May 26, 2020 at 22:05 comment added Big Owls Thanks! Does R1 have an ideal value here? Just something to control false triggering?
May 26, 2020 at 4:13 comment added Big6 I edited the answer to reflect the changes I suggested in my comment
May 26, 2020 at 3:55 vote accept Big Owls
May 26, 2020 at 3:53 comment added Big Owls This simulates pretty good! Can't seem to mark this comment as solution, though! :( Thanks for the suggestions, Big6.
May 26, 2020 at 0:53 history edited Big Owls CC BY-SA 4.0
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May 26, 2020 at 0:22 comment added Big6 Forgot to add, connect the nMOS source directly to GND no need for the 47k resistor, unless you're concerned about over-voltaging the pMOS. And don't connect the nMOS drain to the Q output, like you did in your circuit.
May 26, 2020 at 0:02 comment added Big6 I see the problem in your circuit. Disconnect everything from the Q output, even the 20k resistors. Now, connect Q to the nMOS gate and a 20k resistor from the nMOS gate to GND. Connect the nMOS drain to the pMOS gate. Also from the pMOS gate connect a 20k resistor up to VCC. Leave the load (SSR) as like you have it.
May 25, 2020 at 23:38 history edited Big Owls CC BY-SA 4.0
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May 25, 2020 at 20:43 history edited Big Owls CC BY-SA 4.0
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May 18, 2020 at 20:44 history edited JRE CC BY-SA 4.0
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May 18, 2020 at 20:12 answer added Big6 timeline score: 1
May 18, 2020 at 19:59 comment added Atomique Your 4043 needs pulldown resistors to Vss on its R & S inputs (try 10k). Your 20k resistors need to return to Vdd NOT ground (when the 4081 is HIGH, you want Vgs to be ZERO so the MOSFET is off). With these changes, the load will see +Vdd when the MOSFET is "on" and NO pull-down (basically, open circuit) when it's off -- will that work, given the input specs of your SSR?
May 18, 2020 at 17:58 history edited Big Owls CC BY-SA 4.0
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May 18, 2020 at 17:52 history asked Big Owls CC BY-SA 4.0