I am attempting to implement a latching circuit without software. The results thus far seem promising, but now I want to drive a control line on a solid-state relay using its output as a high-side PNP switch. I opted to use some CMOS logic ICs to simplify the construction of the circuit, so I want to feed one of the IC's output to the gate of a PFET. These CMOS ICs have limited current output, so I thought to try a simple voltage divider to both A.) keep the current output low, and B.) keep Vg negative with respect tp Vs.
Does this design practice seem feasible? If not, what are some recommendations?
ICs: CD4043B cmos r/s latch CD4081B cmos and gate
EDIT: Schematic should read "Vg < Vs" or in this case basically 6V<12V