Timeline for Via layout for decoupling capacitors
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 25, 2020 at 18:50 | answer | added | analogsystemsrf | timeline score: 2 | |
| Aug 25, 2020 at 18:23 | vote | accept | w00t | ||
| Aug 25, 2020 at 8:12 | comment | added | w00t | This will be a 6-8 layer PCB with both PWR and GND planes connected directly to their respective vias | |
| Aug 25, 2020 at 7:54 | answer | added | Puffafish | timeline score: 5 | |
| Aug 25, 2020 at 7:47 | comment | added | Puffafish | How many layers is this PCB? What is your stack up? Do you have a GND pour? | |
| Aug 25, 2020 at 7:26 | history | edited | w00t | CC BY-SA 4.0 |
added 7 characters in body
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| Aug 25, 2020 at 7:21 | history | asked | w00t | CC BY-SA 4.0 |