An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high. The example circuit assumes the D-Flop uses low for reset. If high for reset type, then NOT3 gate can be removed.
simulate this circuitsimulate this circuit – Schematic created using CircuitLab
An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high. The example circuit assumes the D-Flop uses low for reset. If high for reset type, then NOT3 gate can be removed.
simulate this circuit – Schematic created using CircuitLab
An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high. The example circuit assumes the D-Flop uses low for reset. If high for reset type, then NOT3 gate can be removed.
simulate this circuit – Schematic created using CircuitLab
An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high. The example circuit assumes the D-Flop uses low for reset. If high for reset type, then NOT3 gate can be removed.
simulate this circuit – Schematic created using CircuitLab
An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high.
An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high. The example circuit assumes the D-Flop uses low for reset. If high for reset type, then NOT3 gate can be removed.
simulate this circuit – Schematic created using CircuitLab
An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high.
An edge detector like this should do the trick: dual edge detector
An edge detector like this should do the trick: dual edge detector
If the output falling edge needs to be synchronized with the rising edge of the clock, then feed the pulse output into the clock input of a D-Flop and the input clock to the reset input of the D-Flop. D input is tied high.
