Timeline for D-Flip-Flop Hold and Setup Timing Requirements
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
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| Dec 17, 2020 at 17:18 | history | edited | StainlessSteelRat | CC BY-SA 4.0 |
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| Dec 17, 2020 at 17:07 | history | edited | StainlessSteelRat | CC BY-SA 4.0 |
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| Dec 17, 2020 at 17:02 | history | edited | StainlessSteelRat | CC BY-SA 4.0 |
added 374 characters in body
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| Dec 16, 2020 at 15:54 | history | edited | StainlessSteelRat | CC BY-SA 4.0 |
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| Dec 16, 2020 at 15:28 | comment | added | StainlessSteelRat | Tell your professor he must connect FF1Q* to the AND, instead of FF1Q to make it 28ns. I'd do it next term, because he's not going to be happy! But it is 27ns. And he needs a setup time for AND and OR. | |
| Dec 16, 2020 at 15:18 | history | edited | StainlessSteelRat | CC BY-SA 4.0 |
added 297 characters in body
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| Dec 15, 2020 at 22:27 | comment | added | MrCalc | Plus why didn't you take T_in as was done here: electronics.stackexchange.com/questions/537372/… | |
| Dec 15, 2020 at 22:17 | comment | added | MrCalc | The answer is 28 for sure | |
| Dec 15, 2020 at 20:03 | history | answered | StainlessSteelRat | CC BY-SA 4.0 |