Timeline for Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?
Current License: CC BY-SA 4.0
16 events
| when toggle format | what | by | license | comment | |
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| Sep 29, 2022 at 16:20 | history | edited | Null♦ |
edited tags
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| Dec 29, 2020 at 14:56 | history | removed from network questions | Voltage Spike♦ | ||
| S Dec 29, 2020 at 7:57 | history | suggested | Shashank V M | CC BY-SA 4.0 |
changed == to equivalent, to make it easier to read
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| Dec 28, 2020 at 15:13 | review | Suggested edits | |||
| S Dec 29, 2020 at 7:57 | |||||
| S Dec 28, 2020 at 11:34 | history | suggested | Shashank V M |
added verilog, rtl, system-verilog and digital logic tag as it is relevant to the question; original question has verilog tag, if the verilog tag is removed people won't know this question is with respect to which languagei
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| Dec 28, 2020 at 5:25 | comment | added | Shashank V M | @TomCarpenter, will different synthesis tools behave differently? If that is the case, there would be a mismatch between simulation and synthesis. According to Intel's documentation, the width is extended to the size of the output, and that was also what I observed in simulation | |
| Dec 28, 2020 at 3:50 | review | Suggested edits | |||
| S Dec 28, 2020 at 11:34 | |||||
| S Dec 27, 2020 at 16:40 | history | edited | awjlogan |
removed 'assembly' and '*verilog' tags as not relevant
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| S Dec 27, 2020 at 16:40 | history | suggested | Shashank V M |
removed 'assembly' tag as it is not relevant
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| Dec 27, 2020 at 6:53 | review | Suggested edits | |||
| S Dec 27, 2020 at 16:40 | |||||
| Dec 27, 2020 at 5:44 | answer | added | Shashank V M | timeline score: 1 | |
| Dec 27, 2020 at 4:31 | history | became hot network question | |||
| Dec 26, 2020 at 20:37 | answer | added | dave_59 | timeline score: 7 | |
| Dec 26, 2020 at 19:34 | comment | added | Tom Carpenter | Not necessarily. It depends on the width of the signals, and how the synthesis tools decide to expand the widths of BC and AD in the event of the bitshift. | |
| Dec 26, 2020 at 19:14 | comment | added | MrCalc | << means shift . | |
| Dec 26, 2020 at 19:12 | history | asked | MrCalc | CC BY-SA 4.0 |