Electrical Engineering
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Shashank V M

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28 Why would an AND gate need six transistors? Nov 22 '20
5 Simplify the boolean function $$Z=A\bar B \bar{C_i} + \bar A B \bar{C_i} + \bar A\bar B {C_i} + A B {C_i}$$ Sep 5 '20
5 Multiple driver error for SystemVerilog initial value Mar 15
4 Analysis of two D flip-flop designs based on D latches Jan 22
4 Why do we declare the inputs of our design as reg in testbench and outputs as wire? Jan 26
4 '1011' Overlapping (Mealy) Sequence Detector in Verilog Jun 16 '20
3 Does combinational and sequential logic correspond to some mathematical logic systems? Sep 21 '20
3 Viewing verilog enums in iverilog + gtkwave Nov 7 '20
3 How to design Gray code synchronous counters of large widths using SystemVerilog? Sep 4 '20
3 Why does decreasing the voltage also decrease the circuit frequency? Feb 18
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