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Electrical Engineering
Shashank V M's user avatar
Shashank V M's user avatar
Shashank V M's user avatar
Shashank V M
  • Member for 5 years
  • Last seen more than a week ago
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answer
34
Why would an AND gate need six transistors?
Nov 22, 2020
answer
14
Why does decreasing the CMOS supply voltage also decrease the maximum circuit frequency?
Feb 18, 2021
question
10
Why do silicon wafers look rainbow colored?
Jul 3, 2021
question
10
How does an operating system or program detect the CPU model name? [closed]
Jul 21, 2021
answer
6
How does an operating system or program detect the CPU model name?
Jul 21, 2021
answer
5
Why do we declare the inputs of our design as reg in testbench and outputs as wire?
Jan 26, 2021
answer
5
Viewing verilog enums in iverilog + gtkwave
Nov 7, 2020
answer
5
Does combinational and sequential logic correspond to some mathematical logic systems?
Sep 21, 2020
answer
5
Simplify the boolean function $$Z=A\bar B \bar{C_i} + \bar A B \bar{C_i} + \bar A\bar B {C_i} + A B {C_i}$$
Sep 5, 2020
answer
5
Multiple driver error for SystemVerilog initial value
Mar 15, 2021
Top Meta posts
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4
16
Time to burninate [small-electronics]?
9
Can Processor and Microprocessor tag be merged?
6
Should [flipflop] tag be changed to [flip-flop]?
3
Do we need a hardware tag?
3
Burninate [small] tag
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18
Why do more powerful programming languages tend to have slower implementations?