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Shashank V M

  • RTL Design and verification with SystemVerilog and VHDL
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24 Why would an AND gate need six transistors? Nov 22 '20
5 Simplify the boolean function $$Z=A\bar B \bar{C_i} + \bar A B \bar{C_i} + \bar A\bar B {C_i} + A B {C_i}$$ Sep 5 '20
4 '1011' Overlapping (Mealy) Sequence Detector in Verilog Jun 16 '20
3 Does combinational and sequential logic correspond to some mathematical logic systems? Sep 21 '20
3 How to design Gray code synchronous counters of large widths using SystemVerilog? Sep 4 '20
2 How is the Q and Q' determined the first time in JK flip flop? Dec 1 '20
2 Hardware to run a fixed neural network Jul 4 '20
2 Why is an analog circuit more susceptible to noise than a digital one? Oct 21 '20
2 Viewing verilog enums in iverilog + gtkwave Nov 7 '20
2 Rewriting a boolean expression only using NAND Jun 14 '20
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