Timeline for Is (BC + AD)<<16 equivalent to (BC << 16) + (AD <<16)?
Current License: CC BY-SA 4.0
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| Dec 28, 2020 at 15:06 | history | edited | Shashank V M | CC BY-SA 4.0 |
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| Dec 28, 2020 at 13:04 | comment | added | Elliot Alderson | If the question is about Verilog then the important documentation would be the Verilog IEEE standard rather than any single vendor's documentation. It is dangerous to assume that all Verilog tools behave in exactly the same way unless the standard says they must. | |
| Dec 28, 2020 at 5:28 | history | edited | Shashank V M | CC BY-SA 4.0 |
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| Dec 27, 2020 at 6:45 | history | edited | Shashank V M | CC BY-SA 4.0 |
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| Dec 27, 2020 at 5:44 | history | answered | Shashank V M | CC BY-SA 4.0 |