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Feb 9, 2021 at 10:28 comment added Circuit fantasist @LvW, I didn't set myself the goal of deriving the exact formula... I was just looking for quantitative intuitive considerations. In the case, after I assumed an "ideal" rce = 0, and the stage output resistance should be zero because there are two resistors in parallel - Re||rce. In general, looking for such intuitive but real explanations at a low level is a rather ungrateful activity that brings only trouble. It is much more convenient to explain at a "high level" ... then they don't understand you but they respect you-:)
Feb 9, 2021 at 10:10 comment added LvW Thank you. Now - when I see the four-element bridge, how can we derive the output resistance at the most right node (between Rce and Re), which is identical to the emitter ?
Feb 9, 2021 at 10:04 comment added Circuit fantasist @LvW, Yes, this is a conceptual circuit consisting of only four resistors - R1, R2, Rce and Re, and a "galvanometer" Vbe. Rce is the dynamic output resistance of the transistor. Inhirently, it is 'infinitely high differential resistance' but here, because of the voltage-type negative feedvack, it is made to behave as exactly the opposite 'infinitely low differential resistance'. So, for the voltage and current variations it is zero (infinute gm, vertical IV transfer curve).
Feb 9, 2021 at 9:52 comment added LvW Yes - I understand your motivation. But again (just for my understanding) : Am I right that your model (bridge) assumes an IDEAL transistor (infinite gm)?
Feb 9, 2021 at 9:17 comment added Circuit fantasist @LvW, It is only about the DC signal. Regarding the AC variations, it is many times lower because of the low 'rce' in parallel. The "bridge model" can help the OP to imagine what happens in this circuit in a more realustic and intuitive way than the formula and conventional "transistor explanations". Explaining the complex electronic circuits with simpler electrical equivalent and well-known circuits is a power tool for intuitive understanding.
Feb 9, 2021 at 9:10 comment added LvW I must admit that I have some problems to see how your "bridge model" can help to answer the OPs question. If I understand everything well, in your example you arrive at an output resistance of 0.5kOhms in parallel to the contribution from the left side, right? Where is the contribution of the transistors own parameter gm? I think, you have set gm to infinity assuming a balanced bridge, correct?
Feb 9, 2021 at 6:37 history edited Circuit fantasist CC BY-SA 4.0
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Feb 9, 2021 at 6:31 history edited Circuit fantasist CC BY-SA 4.0
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Feb 9, 2021 at 6:25 history edited Circuit fantasist CC BY-SA 4.0
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Feb 9, 2021 at 0:16 history edited Circuit fantasist CC BY-SA 4.0
Added example
Feb 8, 2021 at 23:08 history edited Circuit fantasist CC BY-SA 4.0
About the atmosphere
Feb 8, 2021 at 23:02 history answered Circuit fantasist CC BY-SA 4.0