Skip to main content
Electrical Engineering

Return to Answer

added 2 characters in body
Source Link
Shashank V M
Shashank V M
  • 2.3k
  • 17
  • 54

We can also use Pseudo-NMOS Logic, where youwe can use a single NMOS transistor in the pull-updown network with the gate input of the NMOS transistor tied to GND. This would be slower than CMOS logic for NAND gates but it would have the same speed for NOR gates.

We can also use Pseudo-NMOS Logic, where you can use a single NMOS transistor in the pull-up network with the gate input of the NMOS transistor tied to GND. This would be slower than CMOS logic for NAND gates but it would have the same speed for NOR gates.

We can also use Pseudo-NMOS Logic, where we can use a single NMOS transistor in the pull-down network with the gate input of the NMOS transistor tied to GND. This would be slower than CMOS logic for NAND gates but it would have the same speed for NOR gates.

Source Link
Shashank V M
Shashank V M
  • 2.3k
  • 17
  • 54

We can also use Pseudo-NMOS Logic, where you can use a single NMOS transistor in the pull-up network with the gate input of the NMOS transistor tied to GND. This would be slower than CMOS logic for NAND gates but it would have the same speed for NOR gates.