Timeline for Program FPGA without JTAG?
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 30, 2021 at 0:09 | history | edited | hacktastical | CC BY-SA 4.0 |
added 546 characters in body
|
| Mar 29, 2021 at 22:46 | comment | added | TonyM | Op states Microsemi, not Xilinx. This is just a copy and paste from the Xilinx tech docs, just a big comment really, and not an answer to the question. Downvoting accordingly, I'm afraid. | |
| Mar 29, 2021 at 22:11 | history | edited | hacktastical | CC BY-SA 4.0 |
added 115 characters in body
|
| Mar 29, 2021 at 22:06 | history | answered | hacktastical | CC BY-SA 4.0 |