Timeline for How can I avoid "Minimum Pulse Width" slack violations in Quartus FPGA synthesis?
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 29, 2013 at 8:36 | vote | accept | JCLL | ||
| Jan 28, 2013 at 22:50 | answer | added | isabus | timeline score: 5 | |
| Jan 28, 2013 at 17:23 | comment | added | JCLL | 27 Mhz is set for frequency. The reports seem to say I can go much higher. Concerning duty cycle, I have 50/50 % and I can change this, if advised. | |
| Jan 28, 2013 at 16:54 | comment | added | The Photon | What constraints did you give for the frequency and duty cycle of CLOCK_27? What are the actual frequency and duty cycle you expect in your application? | |
| Jan 28, 2013 at 16:52 | comment | added | JCLL | No, I don't think so. It is about the shape of Clock_27 | |
| Jan 28, 2013 at 16:17 | comment | added | pjc50 | That relates to a clock - it looks like it's too fast? | |
| Jan 28, 2013 at 16:01 | history | edited | Dave Tweed | CC BY-SA 3.0 |
fix formatting of listing
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| Jan 28, 2013 at 15:57 | history | asked | JCLL | CC BY-SA 3.0 |